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| user?s manual pd789405a pd789406a pd789407a pd789407a, 789417a subseries 8-bit single-chip microcontrollers printed in japan document no. u13952ej3v0ud00 (3rd edition) date published april 2003 n cp(k) pd789415a pd789416a pd789417a pd78f9418a 1999, 2003
2 user?s manual u13952ej3v0ud [memo] user?s manual u13952ej3v0ud 3 eeprom and fip are trademarks of nec electronics corporation. windows and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. 4 user ? s manual u13952ej3v0ud these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of november, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1 user ? s manual u13952ej3v0ud 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 fax: 6250-3583 j02.11 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 sucursal en espa ? a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 tyskland filial taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: 6 user?s manual u13952ej3v0ud major revisions in this edition page description pp.38, 39, 41 modification of pin handling of av ref pin and v pp pin in chapter 2 pin functions p.92 addition of note related to feedback resistor in figure 5-3 format of suboscillation mode register pp.112, 113 addition of 6.5 cautions on using 16-bit timer 50 pp.151, 164 addition of (8) input impedance of ani0 to ani6 pins in 10.5 cautions on using 8-bit a/d converter and 11.5 cautions on using 10-bit a/d converter p.154 modification of description of (2) a/d conversion result register 0 (adcr0) in 11.2 configuration of 10-bit a/d converter p.196 addition of description on reading receive data of uart in 13.4.2 asynchronous serial interface (uart) mode p.232 addition of caution in figure 15-2 format of interrupt request flag register p.237 addition of caution in figure 15-7 format of key return mode register 00 p.256 addition of description on pull-up resistor and divider resistor for lcd driving in table 18-1 differences between pd78f9418a and mask rom versions pp.257 to 266 overall revision of contents related to flash memory programming as 18.1 flash memory characteristics pp.278 to 292 addition of chapter 21 electrical specifications pp.293 to 295 addition of chapter 22 characteristics cur ves (reference values) pp.296, 297 addition of chapter 23 package drawings pp.298, 299 addition of chapter 24 recommended soldering conditions pp.300 to 309 overall revision of contents of appendix a development tools deletion of embedded software pp.310 to 313 addition of appendix b notes on target system design the mark shows major revised points. user?s manual u13952ej3v0ud 7 introduction target readers this manual is intended for users who wish to understand the functions of the pd789407a and pd789417a subseries and to design and develop application systems and programs using these microcontrollers. target products: ? pd789407a subseries: pd789405a, pd789406a, and pd789407a ? pd789417a subseries: pd789415a, pd789416a, pd789417a, and pd78f9418a purpose this manual is intended to give users an understanding of the functions described in the organization below. organization the pd 789407a and pd789417a subseries user?s manual is divided into two parts: this manual and instructions (common to the 78k/0s series). pd789407a and pd789417a subseries user?s manual 78k/0s series user?s manual instructions ? pin functions ? internal block functions ? interrupt functions ? other on-chip peripheral functions ? electrical specifications ? cpu function ? instruction set ? explanation of each instruction how to read this manual it is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. ? to understand the functions in general: read this manual in the order of the contents . ? how to interpret the register formats: the name of a bit whose number is enclosed in brackets is reserved for the assembler and is defined for the c compiler by the header file sfrbit.h. ? when you know a register name and want to confirm its details: read appendix c register index . ? to know the 78k/0s series instructions functions in detail: refer to 78k/0s series instructions user?s manual (u11047e). ? to learn the electrical specifications of the pd789407a and pd789417a subseries refer to chapter 21 electrical specifications . 8 user?s manual u13952ej3v0ud conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (overscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd789407a, 789417a subseries user?s manual this manual 78k/0s series instructions user?s manual u11047e documents related to development software tools (user?s manuals) document name document no. operation u14876e language u14877e ra78k0s assembler package structured assembly language u11623e operation u14871e cc78k0s c compiler language u14872e operation (windows tm based) u15373e sm78k series system simulator ver. 2.30 or later external part user open interface specifications u15802e id78k series integrated debugger ver. 2.30 or later operation (windows based) u15185e project manager ver. 3.12 or later (windows based) u14610e documents related to development hardware tools (user?s manuals) document name document no. ie-78k0s-ns in-circuit emulator u13549e ie-78k0s-ns-a in-circuit emulator u15207e ie-789418-ns-em1 emulation board u14364e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. user?s manual u13952ej3v0ud 9 documents related to flash memory writing document name document no. pg-fp3 flash memory programmer user?s manual u13502e pg-fp4 flash memory programmer user?s manual u15260e other related documents document name document no. semiconductor selection guide - products and packages - x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e note see the ?semiconductor device mount manual? webpage (http://www.necel.com/pkg/en/mount/index.html) caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. 10 user?s manual u13952ej3v0ud contents chapter 1 general........................................................................................................... ................23 1.1 features .................................................................................................................. .......................23 1.2 applications .............................................................................................................. ....................23 1.3 ordering information ...................................................................................................... ..............24 1.4 pin configuration (top view) .............................................................................................. ........25 1.5 78k/0s series lineup ...................................................................................................... .............27 1.6 block diagram............................................................................................................. ..................30 1.7 overview of functions ..................................................................................................... ............31 chapter 2 pin functions .................................................................................................... ...........33 2.1 list of pin functions ..................................................................................................... ...............33 2.2 description of pin functions.............................................................................................. .........36 2.2.1 p00 to p03 (port 0) ..................................................................................................... ...................... 36 2.2.2 p20 to p27 (port 2) ..................................................................................................... ...................... 36 2.2.3 p40 to p47 (port 4) ..................................................................................................... ...................... 37 2.2.4 p50 to p53 (port 5) ..................................................................................................... ...................... 37 2.2.5 p60 to p66 (port 6) ..................................................................................................... ...................... 37 2.2.6 p80 to p87 (port 8) ..................................................................................................... ...................... 38 2.2.7 p90 to p93 (port 9) ..................................................................................................... ...................... 38 2.2.8 s0 to s15 ............................................................................................................... ........................... 38 2.2.9 com0 to com3 ............................................................................................................ .................... 38 2.2.10 v lc0 to v lc2 .............................................................................................................................. ...... 38 2.2.11 bias................................................................................................................... ............................. 38 2.2.12 av ref .............................................................................................................................. ............... 38 2.2.13 av dd .............................................................................................................................. ................. 38 2.2.14 av ss .............................................................................................................................. ................. 39 2.2.15 reset .................................................................................................................. .......................... 39 2.2.16 x1, x2 ................................................................................................................. ............................ 39 2.2.17 xt1, xt2............................................................................................................... .......................... 39 2.2.18 v dd0 , v dd1 .............................................................................................................................. ......... 39 2.2.19 v ss0 , v ss1 .............................................................................................................................. ......... 39 2.2.20 v pp ( pd78f9418a only) ............................................................................................................... .39 2.2.21 ic (mask rom version only) ............................................................................................. .............. 40 2.3 pin i/o circuits and recommended connection of unused pins............................................41 chapter 3 cpu architecture ................................................................................................. .....44 3.1 memory space.............................................................................................................. .................44 3.1.1 internal program memory space ........................................................................................... ............ 48 3.1.2 internal data memory space .............................................................................................. ............... 49 3.1.3 special function register (sfr) area.................................................................................... ............. 49 3.1.4 data memory addressing .................................................................................................. ................ 50 3.2 processor registers ....................................................................................................... ..............54 3.2.1 control registers....................................................................................................... ......................... 54 user?s manual u13952ej3v0ud 11 3.2.2 general-purpose registers ............................................................................................... ................. 57 3.2.3 special function registers (sfr) ........................................................................................ ............... 58 3.3 instruction address addressing ............................................................................................ ..... 61 3.3.1 relative addressing ..................................................................................................... ..................... 61 3.3.2 immediate addressing.................................................................................................... ................... 62 3.3.3 table indirect addressing............................................................................................... ................... 63 3.3.4 register addressing..................................................................................................... ..................... 63 3.4 operand address addressing................................................................................................ ..... 64 3.4.1 direct addressing....................................................................................................... ....................... 64 3.4.2 short direct addressing................................................................................................. .................... 65 3.4.3 special function register (sfr) addressing .............................................................................. ........ 66 3.4.4 register addressing..................................................................................................... ..................... 67 3.4.5 register indirect addressing ............................................................................................ ................. 68 3.4.6 based addressing ........................................................................................................ ..................... 69 3.4.7 stack addressing ........................................................................................................ ...................... 69 chapter 4 port functions ................................................................................................... ........ 70 4.1 function of port .......................................................................................................... .................. 70 4.2 configuration of ports .................................................................................................... ............. 72 4.2.1 port 0 .................................................................................................................. .............................. 72 4.2.2 port 2 .................................................................................................................. .............................. 73 4.2.3 port 4 .................................................................................................................. .............................. 78 4.2.4 port 5 .................................................................................................................. .............................. 80 4.2.5 port 6 .................................................................................................................. .............................. 81 4.2.6 port 8 .................................................................................................................. .............................. 83 4.2.7 port 9 .................................................................................................................. .............................. 84 4.3 registers controlling ports ............................................................................................... .......... 85 4.4 operation of ports ........................................................................................................ ................ 88 4.4.1 writing to i/o port..................................................................................................... ......................... 88 4.4.2 reading from i/o port ................................................................................................... .................... 88 4.4.3 arithmetic operation of i/o port ........................................................................................ ................. 88 chapter 5 clock generator .................................................................................................. .... 89 5.1 functions of clock generator .............................................................................................. ....... 89 5.2 configuration of clock generator.......................................................................................... ..... 89 5.3 registers controlling clock generator ..................................................................................... .91 5.4 system clock oscillators.................................................................................................. ........... 94 5.4.1 main system clock oscillator ............................................................................................ ................. 94 5.4.2 subsystem clock oscillator.............................................................................................. .................. 95 5.4.3 examples of incorrect resonator connection.............................................................................. ....... 96 5.4.4 divider................................................................................................................. .............................. 97 5.4.5 when no subsystem clock is used......................................................................................... ........... 97 5.5 operation of clock generator .............................................................................................. ....... 98 5.6 changing setting of system clock and cpu clock .................................................................. 99 5.6.1 time required for switching between system clock and cpu clock.................................................. 99 5.6.2 switching between system clock and cpu clock............................................................................ 100 12 user?s manual u13952ej3v0ud chapter 6 16-bit timer 50 .................................................................................................. ...........101 6.1 function of 16-bit timer 50 ............................................................................................... ........101 6.2 configuration of 16-bit timer 50 .......................................................................................... .....102 6.3 registers controlling 16-bit timer 50 ..................................................................................... .104 6.4 operation of 16-bit timer 50.............................................................................................. ........107 6.4.1 operation as timer interrupt ............................................................................................ ................ 107 6.4.2 operation as timer output ............................................................................................... ................ 109 6.4.3 capture operation ....................................................................................................... .................... 110 6.4.4 16-bit timer counter 50 readout......................................................................................... .............. 111 6.5 cautions on using 16-bit timer 50 ......................................................................................... ..112 6.5.1 restrictions when rewriting 16-bit compare register 50 .................................................................. 112 chapter 7 8-bit timer/event counters 00 to 02..............................................................114 7.1 function of 8-bit timer/event counters 00 to 02 ....................................................................114 7.2 configuration of 8-bit timer/event counters 00 to 02............................................................115 7.3 registers controlling 8-bit timer/event counters 00 to 02 ...................................................118 7.4 operation of 8-bit timer/event counters 00 to 02...................................................................122 7.4.1 operation as interval timer............................................................................................. ................. 122 7.4.2 operation as external event counter (timer 00 and timer 01 only) .................................................. 125 7.4.3 operation as square-wave output (timer 02 only) ......................................................................... .. 126 7.5 cautions on using 8-bit timer/event counters 00 to 02 ........................................................128 chapter 8 watch timer...................................................................................................... ..........129 8.1 functions of watch timer.................................................................................................. ........129 8.2 configuration of watch timer .............................................................................................. .....130 8.3 register controlling watch timer.......................................................................................... ...131 8.4 operation of watch timer.................................................................................................. ........132 8.4.1 operation as watch timer ................................................................................................ ................ 132 8.4.2 operation as interval timer............................................................................................. ................. 132 chapter 9 watchdog timer................................................................................................... .....134 9.1 functions of watchdog timer ............................................................................................... ....134 9.2 configuration of watchdog timer........................................................................................... ..135 9.3 registers controlling watchdog timer ....................................................................................13 6 9.4 operation of watchdog timer ............................................................................................... ....138 9.4.1 operation as watchdog timer ............................................................................................. ............. 138 9.4.2 operation as interval timer............................................................................................. ................. 139 chapter 10 8-bit a/d converter ( pd789407a subseries)..............................................140 10.1 function of 8-bit a/d converter .......................................................................................... ....140 10.2 configuration of 8-bit a/d converter..................................................................................... .140 10.3 registers controlling 8-bit a/d converter .............................................................................143 10.4 operation of 8-bit a/d converter ......................................................................................... ...145 10.4.1 basic operation of 8-bit a/d converter ................................................................................. ......... 145 10.4.2 input voltage and conversion result .................................................................................... .......... 146 10.4.3 operation mode of 8-bit a/d converter .................................................................................. ....... 148 user?s manual u13952ej3v0ud 13 10.5 cautions on using 8-bit a/d converter.................................................................................. 14 9 chapter 11 10-bit a/d converter ( pd789417a subseries) ........................................... 153 11.1 function of 10-bit a/d converter......................................................................................... ... 153 11.2 configuration of 10-bit a/d converter ................................................................................... 1 53 11.3 registers controlling 10-bit a/d converter........................................................................... 156 11.4 operation of 10-bit a/d converter ........................................................................................ .. 158 11.4.1 basic operation of 10-bit a/d converter ................................................................................ ........ 158 11.4.2 input voltage and conversion result .................................................................................... .......... 160 11.4.3 operation mode of 10-bit a/d converter ................................................................................. ...... 161 11.5 cautions on using 10-bit a/d converter................................................................................ 162 chapter 12 comparator ....................................................................................................... ....... 166 12.1 functions of comparator.................................................................................................. ....... 166 12.2 configuration of comparator .............................................................................................. .... 167 12.3 register controlling comparator.......................................................................................... .. 168 12.4 operation of comparator.................................................................................................. ....... 169 chapter 13 serial interface 00 ............................................................................................ .. 171 13.1 functions of serial interface 00 ......................................................................................... ..... 171 13.2 configuration of serial interface 00..................................................................................... ... 172 13.3 registers controlling serial interface 00 ............................................................................... 1 76 13.4 operation of serial interface 00......................................................................................... ...... 183 13.4.1 operation stopped mode ................................................................................................. ............. 183 13.4.2 asynchronous serial interface (uart) mode.............................................................................. .. 185 13.4.3 3-wire serial i/o mode................................................................................................. .................. 198 chapter 14 lcd controller/driver ....................................................................................... 202 14.1 functions of lcd controller/driver ....................................................................................... . 202 14.2 configuration of lcd controller/driver.................................................................................. 2 03 14.3 registers controlling lcd controller/driver ......................................................................... 205 14.4 setting lcd controller/driver............................................................................................ ...... 208 14.5 lcd display data memory .................................................................................................. ..... 208 14.6 common and segment signals............................................................................................... 209 14.7 supplying lcd drive voltages v lc0 , v lc1 , and v lc2 ............................................................. 213 14.8 display modes............................................................................................................ ............... 215 14.8.1 static display example ................................................................................................. ................. 215 14.8.2 two-time-slice display example ......................................................................................... ........... 218 14.8.3 three-time-slice display example ....................................................................................... .......... 221 14.8.4 four-time-slice display example ........................................................................................ ........... 225 chapter 15 interrupt functions............................................................................................. 228 15.1 interrupt function types ................................................................................................. ........ 228 15.2 interrupt sources and configuration...................................................................................... 228 15.3 registers controlling interrupt function ............................................................................... 23 1 15.4 operation of interrupt servicing ......................................................................................... .... 238 15.4.1 non-maskable interrupt acknowledgment operation..................................................................... 238 14 user?s manual u13952ej3v0ud 15.4.2 maskable interrupt acknowledgment operation ............................................................................ 240 15.4.3 multiple interrupt servicing ........................................................................................... ................. 241 15.4.4 putting interrupt requests on hold ..................................................................................... ............ 243 chapter 16 standby function ................................................................................................ ..244 16.1 standby function and configuration .....................................................................................24 4 16.1.1 standby function ....................................................................................................... .................... 244 16.1.2 standby function control register ...................................................................................... ............ 245 16.2 operation of standby function ............................................................................................ ...246 16.2.1 halt mode .............................................................................................................. ..................... 246 16.2.2 stop mode .............................................................................................................. .................... 249 chapter 17 reset function.................................................................................................. ......252 chapter 18 pd78f9418a.................................................................................................................256 18.1 flash memory characteristics............................................................................................. ....257 18.1.1 programming environment................................................................................................ ............ 257 18.1.2 communication mode ..................................................................................................... .............. 258 18.1.3 on-board pin connections............................................................................................... .............. 261 18.1.4 connection when using flash memory writing adapter.................................................................. 264 chapter 19 mask options.................................................................................................... ........267 19.1 mask option for pins ..................................................................................................... ...........267 19.2 mask option for voltage division resistor for lcd driver ..................................................267 chapter 20 instruction set................................................................................................. ......268 20.1 operation ................................................................................................................ ...................268 20.1.1 operand identifiers and description methods ............................................................................ ... 268 20.1.2 description of ?operation? column ...................................................................................... .......... 269 20.1.3 description of ?flag? column ........................................................................................... .............. 269 20.2 operation list........................................................................................................... .................270 20.3 instructions listed by addressing type ................................................................................275 chapter 21 electrical specifications .................................................................................278 chapter 22 characteristics curves (reference values)..........................................293 22.1 characteristics curves for mask rom versions ...................................................................293 22.2 characteristics curves for pd78f9418a ..............................................................................295 chapter 23 package drawings ................................................................................................ 296 chapter 24 recommended soldering conditions ...........................................................298 appendix a development tools ............................................................................................... 300 a.1 software package.......................................................................................................... .............302 a.2 language processing software.............................................................................................. ..302 a.3 control software .......................................................................................................... ..............303 user?s manual u13952ej3v0ud 15 a.4 flash memory writing tools ................................................................................................ ..... 303 a.5 debugging tools (hardware)................................................................................................ .... 304 a.6 debugging tools (software) ................................................................................................ ..... 305 a.7 package drawings of conversion socket and conversion adapter .................................... 306 a.7.1 package drawing and recommended footprint of conversion socket (ev-9200gc-80) ................. 306 a.7.2 package drawing of conversion adapter (tgk-080sdw) .............................................................. 308 a.7.3 package drawing of conversion adapter (tgc-080sbp) ............................................................... 309 appendix b notes on target system design ................................................................... 310 appendix c register index .................................................................................................. ....... 314 c.1 register index (alphabetic order of register name) ............................................................. 314 c.2 register index (alphabetic order of register symbol).......................................................... 316 appendix d revision history ................................................................................................ ..... 318 16 user?s manual u13952ej3v0ud list of figures (1/5) figure no. title page 2-1 pin i/o circuits ............................................................................................................ ................................ 42 3-1 memory map ( pd789405a and pd789415a) ......................................................................................... 44 3-2 memory map ( pd789406a and pd789416a) ......................................................................................... 45 3-3 memory map ( pd789407a and pd789417a) ......................................................................................... 46 3-4 memory map ( pd78f9418a) .................................................................................................................... 47 3-5 data memory addressing ( pd789405a and pd789415a)...................................................................... 50 3-6 data memory addressing ( pd789406a and pd789416a)...................................................................... 51 3-7 data memory addressing ( pd789407a and pd789417a)...................................................................... 52 3-8 data memory addressing ( pd78f9418a)................................................................................................. 53 3-9 program counter configuration ............................................................................................... ................... 54 3-10 program status word configuration .......................................................................................... ................. 54 3-11 stack pointer configuration ................................................................................................ ........................ 56 3-12 data saved to stack memory................................................................................................. ..................... 56 3-13 data restored from stack memory ............................................................................................ ................. 56 3-14 general-purpose register configuration ..................................................................................... ............... 57 4-1 port types.................................................................................................................. ................................. 70 4-2 block diagram of p00 to p03 ................................................................................................. ..................... 72 4-3 block diagram of p20........................................................................................................ .......................... 73 4-4 block diagram of p21........................................................................................................ .......................... 74 4-5 block diagram of p22 and p24 ................................................................................................ ................... 75 4-6 block diagram of p23........................................................................................................ .......................... 76 4-7 block diagram of p25 to p27 ................................................................................................. ..................... 77 4-8 block diagram of p40 to p45 ................................................................................................. ..................... 78 4-9 block diagram of p46 and p47 ................................................................................................ ................... 79 4-10 block diagram of p50 to p53 ................................................................................................ ...................... 80 4-11 block diagram of p60 and p61 ............................................................................................... .................... 81 4-12 block diagram of p62 to p66 ................................................................................................ ...................... 82 4-13 block diagram of p80 to p87 ................................................................................................ ...................... 83 4-14 block diagram of p90 to p93 ................................................................................................ ...................... 84 4-15 format of port mode register ............................................................................................... ...................... 86 4-16 format of pull-up resistor option register 0 ............................................................................... .............. 86 4-17 format of pull-up resistor option register 1 ............................................................................... .............. 87 4-18 format of pull-up resistor option register 2 ............................................................................... .............. 87 5-1 block diagram of clock generator............................................................................................ .................. 90 5-2 format of processor clock control register.................................................................................. ............. 91 5-3 format of suboscillation mode register ...................................................................................... ............... 92 5-4 format of subclock control register ......................................................................................... ................. 93 5-5 external circuit of main system clock oscillator ............................................................................ ............ 94 5-6 external circuit of subsystem clock oscillator .............................................................................. ............. 95 5-7 examples of incorrect resonator connection.................................................................................. ........... 96 5-8 switching between system clock and cpu clock ................................................................................ ... 100 user?s manual u13952ej3v0ud 17 list of figures (2/5) figure no. title page 6-1 block diagram of 16-bit timer 50 ............................................................................................ ..................102 6-2 format of 16-bit timer mode control register 50 ............................................................................. ........105 6-3 format of port mode register 2.............................................................................................. ...................106 6-4 settings of 16-bit timer mode control register 50 for timer interrupt operation .....................................107 6-5 timing of timer interrupt operation ......................................................................................... ..................108 6-6 settings of 16-bit timer mode control register 50 for timer output operation........................................109 6-7 timer output timing ......................................................................................................... .........................109 6-8 settings of 16-bit timer mode control register 50 for capture operation ................................................110 6-9 capture operation timing (both edges of cpt5 pin are specified) .........................................................110 6-10 readout timing of 16-bit timer counter 50 .................................................................................. ............111 7-1 block diagram of 8-bit timer/event counter 00 ............................................................................... .........116 7-2 block diagram of 8-bit timer/event counter 01 ............................................................................... .........116 7-3 block diagram of 8-bit timer 02 ............................................................................................. ...................117 7-4 format of 8-bit timer mode control register 00 .............................................................................. .........118 7-5 format of 8-bit timer mode control register 01 .............................................................................. .........119 7-6 format of 8-bit timer mode control register 02 .............................................................................. .........120 7-7 format of port mode register 2.............................................................................................. ...................121 7-8 interval timer operation timing of timer 00 and timer 01 .................................................................... ...123 7-9 interval timer operation timing of timer 02 ................................................................................. ............124 7-10 external event counter operation timing (with rising edge specified) ...................................................125 7-11 square-wave output timing.................................................................................................. ....................127 7-12 start timing of 8-bit timer counters 00, 01, and 02........................................................................ ..........128 7-13 external event counter operation timing .................................................................................... .............128 8-1 block diagram of watch timer ................................................................................................ ..................129 8-2 format of watch timer mode control register................................................................................. .........131 8-3 watch timer/interval timer operation timing ................................................................................. ..........133 9-1 block diagram of watchdog timer ............................................................................................. ...............135 9-2 format of timer clock selection register 2 .................................................................................. ............136 9-3 format of watchdog timer mode register ...................................................................................... ..........137 10-1 block diagram of 8-bit a/d converter....................................................................................... .................141 10-2 format of a/d converter mode register 0.................................................................................... .............143 10-3 format of a/d input selection register 0................................................................................... ................144 10-4 basic operation of 8-bit a/d converter ..................................................................................... ................146 10-5 relationship between analog input voltage and a/d conversion result..................................................147 10-6 software-started a/d conversion ............................................................................................ ..................148 10-7 how to reduce current consumption in standby mode.......................................................................... ..149 10-8 conversion result readout timing (when conversion result is undefined value).................................150 10-9 conversion result readout timing (when conversion result is normal value)......................................150 10-10 analog input pin processing ............................................................................................... .......................151 10-11 a/d conversion end interrupt request generation timing .................................................................... ...152 18 user?s manual u13952ej3v0ud list of figures (3/5) figure no. title page 10-12 av dd pin processing ................................................................................................................ ................. 152 11-1 block diagram of 10-bit a/d converter...................................................................................... ............... 154 11-2 format of a/d converter mode register 0.................................................................................... ............ 156 11-3 format of a/d input selection register 0................................................................................... ............... 157 11-4 basic operation of 10-bit a/d converter.................................................................................... ............... 159 11-5 relationship between analog input voltage and a/d conversion result................................................. 160 11-6 software-started a/d conversion ............................................................................................ ................. 161 11-7 how to reduce current consumption in standby mode.......................................................................... . 162 11-8 conversion result readout timing (when conversion result is undefined value) ................................ 163 11-9 conversion result readout timing (when conversion result is normal value)..................................... 163 11-10 analog input pin processing ............................................................................................... ...................... 164 11-11 a/d conversion end interrupt request generation timing .................................................................... .. 165 11-12 av dd pin processing ................................................................................................................ ................. 165 12-1 block diagram of comparator ................................................................................................ ................... 167 12-2 format of comparator mode register 0....................................................................................... ............. 168 12-3 settings of comparator mode register 0 for comparator operation ........................................................ 169 12-4 settings of external interrupt mode register 1 at intcmp0 occurrence ................................................. 169 12-5 comparator operation timing................................................................................................ ................... 170 13-1 block diagram of serial interface 00....................................................................................... .................. 173 13-2 block diagram of baud rate generator....................................................................................... ............. 174 13-3 format of serial operation mode register 00................................................................................ ........... 176 13-4 format of asynchronous serial interface mode register 00................................................................... .. 177 13-5 format of asynchronous serial interface status register 00 ................................................................. .. 179 13-6 format of baud rate generator control register 00.......................................................................... ...... 180 13-7 format of asynchronous serial interface transmit/receive data ............................................................ 19 1 13-8 asynchronous serial interface transmission completion interrupt timing............................................... 193 13-9 asynchronous serial interface reception completion interrupt timing.................................................... 194 13-10 receive error timing...................................................................................................... ........................... 195 13-11 3-wire serial i/o mode timing ............................................................................................. ..................... 201 14-1 block diagram of lcd controller/driver..................................................................................... ............... 204 14-2 format of lcd display mode register 0...................................................................................... ............. 205 14-3 format of lcd port selector 0 .............................................................................................. .................... 206 14-4 format of lcd clock control register 0..................................................................................... .............. 207 14-5 relationship between lcd display data memory contents and segment/common outputs ................. 208 14-6 common signal waveforms.................................................................................................... .................. 211 14-7 voltages and phases of common and segment signals.......................................................................... 212 14-8 examples of lcd drive power connections (with on-chip voltage divider resistors) ........................... 214 14-9 static lcd display pattern and electrode connections....................................................................... ..... 215 14-10 example of connecting static lcd panel.................................................................................... ............. 216 14-11 static lcd drive waveform examples........................................................................................ .............. 217 user?s manual u13952ej3v0ud 19 list of figures (4/5) figure no. title page 14-12 two-time-slice lcd display pattern and electrode connections ............................................................21 8 14-13 example of connecting two-time-slice lcd panel............................................................................ ......219 14-14 two-time-slice lcd drive waveform examples (1/2 bias method) .........................................................220 14-15 three-time-slice lcd display pattern and electrode connections..........................................................22 1 14-16 example of connecting three-time-slice lcd panel .......................................................................... .....222 14-17 three-time-slice lcd drive waveform examples (1/2 bias method).......................................................223 14-18 three-time-slice lcd drive waveform examples (1/3 bias method).......................................................224 14-19 four-time-slice lcd display pattern and electrode connections............................................................2 25 14-20 example of connecting four-time-slice lcd panel ........................................................................... ......226 14-21 four-time-slice lcd drive waveform examples (1/3 bias method).........................................................227 15-1 basic configuration of interrupt function.................................................................................. .................230 15-2 format of interrupt request flag register.................................................................................. ...............232 15-3 format of interrupt mask flag register ..................................................................................... ................233 15-4 format of external interrupt mode register 0............................................................................... .............234 15-5 format of external interrupt mode register 1............................................................................... .............235 15-6 configuration of program status word ....................................................................................... ...............236 15-7 format of key return mode register 00 ...................................................................................... .............237 15-8 block diagram of falling edge detector ..................................................................................... ...............237 15-9 flowchart of non-maskable interrupt request acknowledgment ..............................................................239 15-10 timing of non-maskable interrupt request acknowledgment ................................................................... 239 15-11 non-maskable interrupt request acknowledgment............................................................................. ......239 15-12 interrupt acknowledgment program algorithm................................................................................ ...........240 15-13 interrupt request acknowledgment timing (example: mov a, r) .............................................................24 1 15-14 interrupt request acknowledgment timing (when interrupt request flag is generated in final clock under execution) ................................................................................... ........241 15-15 example of multiple interrupt ............................................................................................. ........................242 16-1 format of oscillation stabilization time selection register................................................................ .......245 16-2 releasing halt mode by interrupt........................................................................................... .................247 16-3 releasing halt mode by reset input ......................................................................................... ...........248 16-4 releasing stop mode by interrupt ........................................................................................... ................250 16-5 releasing stop mode by reset input......................................................................................... ...........251 17-1 block diagram of reset function............................................................................................ ...................252 17-2 reset timing by reset input ................................................................................................ ...................253 17-3 reset timing by overflow in watchdog timer................................................................................. ..........253 17-4 reset timing by reset input in stop mode................................................................................... ........253 18-1 environment for writing program to flash memory ............................................................................ .......257 18-2 communication mode selection format ........................................................................................ ............258 18-3 example of connection with dedicated flash programmer...................................................................... .259 18-4 v pp pin connection example ........................................................................................................ .............261 18-5 signal conflict (serial interface input pin) ............................................................................... ..................262 20 user?s manual u13952ej3v0ud list of figures (5/5) figure no. title page 18-6 malfunction of another device .............................................................................................. .................... 262 18-7 signal conflict (reset pin)................................................................................................ ...................... 263 18-8 example of flash memory writing adapter connection when using 3-wire serial i/o mode.................. 264 18-9 example of flash memory writing adapter connection when using uart mode .................................. 265 18-10 example of flash memory writing adapter connection when using pseudo 3-wire mode (when p0 is used) .............................................................................................................. ...................... 266 a-1 development tools ........................................................................................................... ........................ 301 a-2 package drawing of ev-9200gc-80 (for reference) ............................................................................. .. 306 a-3 recommended footprint of ev-9200gc-80 (for reference) .................................................................... 307 a-4 package drawing of tgk-080sdw (for reference) ............................................................................... .. 308 a-5 package drawing of tgc-080sbp (for reference) ............................................................................... ... 309 b-1 distance between in-circuit emulator and conversion socket (80gc).................................................... 310 b-2 connection condition of target system (np-80gc-tq).......................................................................... . 311 b-3 distance between in-circuit emulator and conversion adapter (80gk) .................................................. 312 b-4 connection condition of target system (np-80gk)............................................................................. .... 313 user?s manual u13952ej3v0ud 21 list of tables (1/2) table no. title page 2-1 types of pin i/o circuits ................................................................................................... ...........................41 3-1 internal rom capacity....................................................................................................... ..........................48 3-2 vector table................................................................................................................ .................................48 3-3 special function register list .............................................................................................. .......................59 4-1 port functions .............................................................................................................. ................................71 4-2 configuration of port ....................................................................................................... .............................72 4-3 port mode register and output latch settings when using alternate functions .......................................85 5-1 configuration of clock generator............................................................................................ .....................89 5-2 maximum time required for switching cpu clock ............................................................................... ......99 6-1 configuration of 16-bit timer 50 ............................................................................................ ....................102 6-2 interval time of 16-bit timer 50............................................................................................ .....................107 6-3 settings of capture edge .................................................................................................... .......................110 7-1 interval time of 8-bit timer/event counter 00............................................................................... ............114 7-2 interval time of 8-bit timer/event counter 01............................................................................... ............114 7-3 interval time of 8-bit timer 02............................................................................................. ......................114 7-4 square-wave output range of 8-bit timer 02 .................................................................................. ........115 7-5 configuration of 8-bit timer/event counters 00 to 02 ........................................................................ .......115 7-6 interval time of 8-bit timer/event counter 00............................................................................... ............122 7-7 interval time of 8-bit timer/event counter 01............................................................................... ............122 7-8 interval time of 8-bit timer 02............................................................................................. ......................123 7-9 square-wave output range of 8-bit timer 02 .................................................................................. ........126 8-1 interval time of interval timer ............................................................................................. ......................130 8-2 configuration of watch timer ................................................................................................ ....................130 8-3 interval time of interval timer ............................................................................................. ......................132 9-1 program loop detection time of watchdog timer ............................................................................... .....134 9-2 interval time ............................................................................................................... ...............................134 9-3 configuration of watchdog timer ............................................................................................. .................135 9-4 program loop detection time of watchdog timer ............................................................................... .....138 9-5 interval time of interval timer ............................................................................................. ......................139 10-1 configuration of 8-bit a/d converter....................................................................................... ...................140 11-1 configuration of 10-bit a/d converter...................................................................................... ..................153 12-1 intcmp0 valid edges ........................................................................................................ .......................169 13-1 configuration of serial interface 00....................................................................................... .....................172 22 user?s manual u13952ej3v0ud list of tables (2/2) table no. title page 13-2 operation mode settings of serial interface 00 ............................................................................. ........... 178 13-3 example of relationship between main system clock and baud rate.................................................... 181 13-4 relationship between asck pin input frequency and baud rate (when brgc00 is set to 80h)......... 182 13-5 example of relationship between main system clock and baud rate.................................................... 189 13-6 relationship between asck pin input frequency and baud rate (when brgc00 is set to 80h)......... 190 13-7 receive error causes ....................................................................................................... ........................ 195 14-1 maximum number of pixels ................................................................................................... ................... 202 14-2 configuration of lcd controller/driver..................................................................................... ................. 203 14-3 frame frequencies (hz) ..................................................................................................... ...................... 207 14-4 com signals ................................................................................................................ ............................. 209 14-5 lcd drive voltage.......................................................................................................... ........................... 210 14-6 lcd drive voltages (with on-chip voltage divider resistors) ................................................................ . 213 14-7 select and deselect voltages (com0)........................................................................................ .............. 215 14-8 select and deselect voltages (com0 and com1) ............................................................................... .... 218 14-9 select and deselect voltages (com0 to com2) ................................................................................ ...... 221 14-10 select and deselect voltages (com0 to com3) ............................................................................... ....... 225 15-1 interrupt source list...................................................................................................... ............................ 229 15-2 flags corresponding to interrupt request signal name....................................................................... .... 231 15-3 time from generation of maskable interrupt request to servicing .......................................................... 24 0 16-1 halt mode operating status ................................................................................................. .................. 246 16-2 operation after release of halt mode....................................................................................... ............. 248 16-3 stop mode operating status................................................................................................. .................. 249 16-4 operation after release of stop mode ....................................................................................... ............ 251 17-1 hardware status after reset................................................................................................ ..................... 254 18-1 differences between pd78f9418a and mask rom versions................................................................ 256 18-2 communication mode list.................................................................................................... ..................... 258 18-3 pin connection list ........................................................................................................ ........................... 260 19-1 selection of mask option for pins .......................................................................................... ................... 267 19-2 combination of selectable voltage division resistor ........................................................................ ....... 267 20-1 operand identifiers and description methods ................................................................................ ........... 268 24-1 surface mounting type soldering conditions ................................................................................. .......... 298 user?s manual u13952ej3v0ud 23 chapter 1 general 1.1 features rom and ram capacities item program memory data memory part number internal high-speed ram lcd data ram pd789405a, 789415a rom 12 kb 512 bytes 28 4 bits pd789406a, 789416a 16 kb pd789407a, 789417a 24 kb pd78f9418a flash memory 32 kb minimum instruction execution time can be changed from high speed (0.4 s: @ 5.0 mhz operation with main system clock) to ultra low speed (122 s: @ 32.768 khz operation with subsystem clock) 43 i/o ports serial interface channel: switchable between 3-wire serial i/o and uart modes lcd controller/driver: up to 28 segment signal outputs up to 4 common signal outputs bias switchable between 1/2 and 1/3 seven a/d converters with an 8-bit resolution (for pd789407a subseries only) seven a/d converters with a 10-bit resolution (for pd789417a subseries only) six timers: 16-bit timer two 8-bit timer/event counters 8-bit timer watch timer watchdog timer 17 vectored interrupt sources power supply voltage: v dd = 1.8 to 5.5 v operating ambient temperature: t a = ?40 to +85 c 1.2 applications aps compact cameras, manometers, rice cookers, etc. chapter 1 general 24 user?s manual u13952ej3v0ud 1.3 ordering information part number package internal rom pd789405agc-xxx-8bt 80-pin plastic qfp (14 x 14) mask rom pd789405agk-xxx-9eu 80-pin plastic tqfp (fine pitch) (12 x 12) mask rom pd789406agc-xxx-8bt 80-pin plastic qfp (14 x 14) mask rom pd789406agk-xxx-9eu 80-pin plastic tqfp (fine pitch) (12 x 12) mask rom pd789407agc-xxx-8bt 80-pin plastic qfp (14 x 14) mask rom pd789407agk-xxx-9eu 80-pin plastic tqfp (fine pitch) (12 x 12) mask rom pd789415agc-xxx-8bt 80-pin plastic qfp (14 x 14) mask rom pd789415agk-xxx-9eu 80-pin plastic tqfp (fine pitch) (12 x 12) mask rom pd789416agc-xxx-8bt 80-pin plastic qfp (14 x 14) mask rom pd789416agk-xxx-9eu 80-pin plastic tqfp (fine pitch) (12 x 12) mask rom pd789417agc-xxx-8bt 80-pin plastic qfp (14 x 14) mask rom pd789417agk-xxx-9eu 80-pin plastic tqfp (fine pitch) (12 x 12) mask rom pd78f9418agc-8bt 80-pin plastic qfp (14 x 14) flash memory pd78f9418agk-9eu 80-pin plastic tqfp (fine pitch) (12 x 12) flash memory remark xxx indicates rom code suffix. chapter 1 general user?s manual u13952ej3v0ud 25 1.4 pin configuration (top view) 80-pin plastic qfp (14 x 14) 80-pin plastic tqfp (fine pitch) (12 x 12) pd789405agc- xxx -8bt pd789405agk- xxx -9eu pd789406agc- xxx -8bt pd789406agk- xxx -9eu pd789407agc- xxx -8bt pd789407agk- xxx -9eu pd789415agc- xxx -8bt pd789415agk- xxx -9eu pd789416agc- xxx -8bt pd789416agk- xxx -9eu pd789417agc- xxx -8bt pd789417agk- xxx -9eu pd78f9418agc-8bt pd78f9418agk-9eu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 v dd1 bias v lc0 v lc1 v lc2 v ss1 com0 com1 com2 com3 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 p50 p51 p52 p53 p20/sck/asck p21/so/txd p22/si/rxd p23/cmptout0/to2 p24/intp0/ti0 p25/intp1/ti1 p26/intp2/to5 p27/intp3/cpt5 av ss p60/ani0/cmpin0 p61/ani1/cmpref0 p62/ani2 p63/ani3 p64/ani4 p65/ani5 p66/ani6 s10 s11 s12 s13 s14 s15 p93/s16 p92/s17 p91/s18 p90/s19 p87/s20 p86/s21 p85/s22 p84/s23 p83/s24 p82/s25 p81/s26 p80/s27 av dd av ref p40/kr0 p41/kr1 p42/kr2 p43/kr3 p44/kr4 p45/kr5 ic (v pp ) xt1 xt2 v dd0 v ss0 x1 x2 reset p46 p47 p00 p01 p02 p03 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 cautions 1. connect the ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect the av dd pin to v dd0 . 3. connect the av ss pin to v ss0 . remark the parenthesized values apply to the pd78f9418a. chapter 1 general 26 user ? s manual u13952ej3v0ud ani0 to ani6: analog input p60 to p66: port 6 asck: asynchronous serial input p80 to p87: port 8 av dd : analog power supply p90 to p93: port 9 av ref : analog reference voltage reset: reset av ss : analog ground rxd: receive data bias: lcd power supply bias control s0 to s27: segment output cmpin0: comparator input sck: serial clock cmpref0: comparator reference si: serial input cmptout0: comparator output so: serial output com0 to com3: common output ti0, ti1: timer input cpt5: capture trigger input to2, to5: timer output ic: internally connected txd: transmit data intp0 to intp3: interrupt from peripherals v dd0 , v dd1 : power supply kr0 to kr5: key return v lc0 to v lc2 : lcd power supply p00 to p03: port 0 v pp : programming power supply p20 to p27: port 2 v ss0 , v ss1 : ground p40 to p47: port 4 x1, x2: crystal (main system clock) p50 to p53: port 5 xt1, xt2: crystal (subsystem clock) chapter 1 general user ? s manual u13952ej3v0ud 27 1.5 78k/0s series lineup the products in the 78k/0s series are listed below. the names enclosed in boxes are subseries names. 52-pin sio + resistance division method lcd (24 4) 8-bit a/d + internal voltage boosting method lcd (23 4) pd789327 lcd drive 80-pin 80-pin pd789436 pd789446 pd789426 pd789456 pd789417a pd789407a pd789316 pd789467 pd789306 pd789426 with 10-bit a/d pd789860 with enhanced timer function, sio, and expanded rom and ram pd789446 with 10-bit a/d sio + 8-bit a/d + resistance division method lcd (28 4) sio + 8-bit a/d + internal voltage boosting method lcd (15 4) pd789407a with 10-bit a/d sio + 8-bit a/d + internal voltage boosting method lcd (5 4) rc oscillation version of pd789306 sio + internal voltage boosting method lcd (24 4) 64-pin 64-pin 52-pin 64-pin 64-pin 64-pin sio + 10-bit a/d + internal voltage boosting method lcd (28 4) 80-pin sio + 8-bit a/d + resistance division method lcd (28 4) 80-pin pd789479 pd789489 64-pin products under development products in mass production small-scale package, general-purpose applications 78k/0s series 28-pin pd789014 with enhanced timer function and expanded rom and ram on-chip uart and capable of low-voltage (1.8 v) operation pd789074 with subsystem clock added inverter control 44-pin pd789842 on-chip inverter controller and uart pd789146 pd789156 44-pin small-scale package, general-purpose applications and a/d function 44-pin 30-pin 30-pin 30-pin 30-pin pd789124a pd789134a pd789177 pd789167 30-pin 30-pin pd789104a pd789114a pd789167 with 10-bit a/d pd789104a with enhanced timer function pd789124a with 10-bit a/d rc oscillation version of pd789104a pd789104a with 10-bit a/d pd789026 with 8-bit a/d and multiplier added pd789104a with eeprom added pd789146 with 10-bit a/d pd789177y pd789167y y subseries supports smb. usb 88-pin pd789830 pd789835 144-pin uart + dot lcd (40 16) uart + 8-bit a/d + dot lcd (total display outputs: 96) 42-/44-pin 44-pin 30-pin 20-pin 20-pin pd789026 with enhanced timer function rc oscillation version of pd789052 vfd drive 52-pin 64-pin pd789871 on-chip vfd controller (total display outputs: 25) meter control pd789881 uart + resistance division method lcd (26 4) 30-pin pd789074 with enhanced timer function and expanded rom and ram 44-pin pd789800 for pc keyboard. on-chip usb function keyless entry 20-pin 20-pin 30-pin on-chip poc and key return circuit rc oscillation version of pd789860 on-chip bus controller 30-pin pd789850 on-chip can controller pd789074 pd789088 pd789062 pd789014 pd789046 pd789026 pd789052 pd789860 pd789861 pd789862 pd789860 without eeprom tm , poc, and lvi remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same. chapter 1 general 28 user ? s manual u13952ej3v0ud the major functional differences between the subseries are listed below. series for general-purpose applications and lcd drive timer v dd function subseries rom capacity (bytes) 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min.value remarks pd789046 16 k 1 ch pd789026 4 k to 16 k 1 ch 34 pd789088 16 k to 32 k 3 ch pd789074 2 k to 8 k 1 ch 1 ch 24 pd789014 2 k to 4 k 2 ch ? ? 1 ch ?? 1 ch (uart: 1 ch) 22 1.8 v ? pd789062 4 k ? 14 rc-oscillation version small- scale package, general- purpose applica- tions pd789052 ? pd789177 ? 8 ch pd789167 16 k to 24 k 3 ch 1 ch 8 ch ? 31 ? pd789156 ? 4 ch pd789146 8 k to 16 k 4 ch ? on-chip eeprom pd789134a ? 4 ch pd789124a 4 ch ? rc-oscillation version pd789114a ? 4 ch small- scale package, general- purpose applica- tions + a/d converter pd789104a 2 k to 8 k 1 ch 1 ch ? 1 ch 4 ch ? 1 ch (uart: 1 ch) 20 1.8 v ? pd789835 24 k to 60 k 6 ch ? 3 ch 37 1.8 v note pd789830 24 k 1 ch ? 1 ch (uart: 1 ch) 30 2.7 v dot lcd supported pd789489 32 k to 48 k ? 8 ch pd789479 24 k to 48 k 8 ch ? 2 ch (uart: 1 ch) 45 pd789417a ? 7 ch pd789407a 12 k to 24 k 3 ch 1 ch 1 ch 1 ch 7 ch ? 1 ch (uart: 1 ch) 43 1.8 v ? pd789456 ? 6 ch pd789446 6 ch ? 30 pd789436 ? 6 ch pd789426 12 k to 16 k 6 ch 40 pd789316 rc-oscillation version pd789306 8 k to 16 k ? 2 ch (uart: 1 ch) 23 pd789467 1 ch ? 18 lcd drive pd789327 4 k to 24 k 2 ch ? ? ? 1 ch 21 ? note flash memory version: 3.0 v chapter 1 general user ? s manual u13952ej3v0ud 29 series for assp timer v dd function subseries rom capacity (bytes) 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min.value remarks usb pd789800 8 k 2 ch ?? 1 ch ?? 2 ch (usb: 1 ch) 31 4.0 v ? inverter control pd789842 8 k to 16 k 3 ch note 1 1 ch 1 ch 8 ch ? 1 ch (uart: 1 ch) 30 4.0 v ? on-chip bus controller pd789850 16 k 1 ch 1 ch ? 1 ch 4 ch ? 2 ch (uart: 1 ch) 18 4.0 v ? pd789861 1.8 v rc-oscillation version, on-chip eeprom pd789860 4 k 2 ch ?? 1 ch ?? ? 14 keyless entry pd789862 16 k 1 ch 2 ch 1 ch (uart: 1 ch) 22 on-chip eeprom vfd drive pd789871 4 k to 8 k 3 ch ? 1 ch 1 ch ?? 1 ch 33 2.7 v ? meter control pd789881 16 k 2 ch 1 ch ? 1 ch ?? 1 ch (uart: 1 ch) 28 2.7 v note 2 ? notes 1. 10-bit timer: 1 channel 2. flash memory version: 3.0 v chapter 1 general 30 user ? s manual u13952ej3v0ud 1.6 block diagram 78k/0s cpu core rom (flash memory) ram v dd0 v dd1 v ss0 v ss1 ic (v pp ) ti0/p24 8-bit timer event/counter 00 p00 to p03 port 0 p20 to p27 port 2 p40 to p47 port 4 p50 to p53 port 5 p60 to p66 port 6 p80 to p87 port 8 p90 to p93 port 9 system control ti1/p25 8-bit timer event/counter 01 to2/p23 8-bit timer 02 to5/p26 cpt5/p27 16-bit timer 50 watch timer watchdog timer serial interface sck/asck/p20 si/rxd/p22 so/txd/p21 comparator cmptout0/p23 cmpref0/p61 cmpin0/p60 a/d converter ani0/p60 ani2/p62 to ani6/p66 ani1/p61 av dd av ss av ref v lc0 to v lc2 bias s0 to s15 s16/p93 to s19/p90 s20/p87 to s27/p80 com0 to com3 lcd controller/driver reset x1 x2 xt1 xt2 interrupt control intp0/p24 intp1/p25 intp2/p26 intp3/p27 kr0/p40 to kr5/p45 remarks 1. the internal rom capacity varies depending on the product. 2. the parenthesized values apply to the pd78f9418a. chapter 1 general user ? s manual u13952ej3v0ud 31 1.7 overview of functions part number item pd789405a pd789415a pd789406a pd789416a pd789407a pd789417a pd78f9418a internal memory rom mask rom flash memory 12 kb 16 kb 24 kb 32 kb high-speed ram 512 bytes lcd data ram 28 4 bits minimum instruction execution time 0.4/1.6 s (@ 5.0 mhz operation with main system clock) 122 s (@ 32.768 khz operation with sub system clock) general-purpose registers 8 bits 8 registers instruction set 16-bit operations bit manipulation (set, reset, and test) i/o ports total of 43 port pins 7 cmos input pins 32 cmos i/o pins 4 n-ch open-drain pins (12 v withstanding voltage) a/d converters seven channels with 8-bit resolution (for pd789407a subseries) seven channels with 10-bit resolution (for pd789417a subseries) comparator with timer output control function serial interface switchable between 3-wire serial i/o and uart modes lcd controller/driver up to 28 segment signal outputs up to 4 common signal outputs bias switchable between 1/2 and 1/3 timers 16-bit timer: 1 channel 8-bit timer: 1 channel 8-bit timer/event counters: 2 channels watch timer: 1 channel watchdog timer: 1 channel timer output 2 outputs maskable internal: 11, external: 5 non-maskable internal: 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to + 85 c package 80-pin plastic qfp (14 x 14) 80-pin plastic tqfp (fine pitch) (12 x 12) vectored interrupt sources chapter 1 general 32 user ? s manual u13952ej3v0ud an outline of the timer is shown below. 16-bit timer 50 8-bit timer/event counters 00, 01 8-bit timer 02 watch timer watchdog timer interval timer ? 1 channel 1 channel 1 channel note 1 1 channel note 2 operation mode external event counter ? 1 channel ??? timer outputs 1 ? 1 ?? square-wave outputs ?? 1 ?? capture 1 input ???? function interrupt sources 11122 notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer has watchdog timer and interval timer functions. however, use the watchdog timer by selecting either the watchdog timer function or interval timer function. user?s manual u13952ej3v0ud 33 chapter 2 pin functions 2.1 list of pin functions (1) port pins pin name i/o function after reset alternate function p00 to p03 i/o port 0. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 0 (pu0). input ? p20 sck/asck p21 so/txd p22 si/rxd p23 cmptout0/to2 p24 intp0/ti0 p25 intp1/ti1 p26 intp2/to5 p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 1 (pu1). input intp3/cpt5 p40 to p45 kr0 to kr5 p46, p47 i/o port 4. 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 0 (pu0). input ? p50 to p53 i/o port 5. 4-bit n-ch open-drain i/o port. input/output can be specified in 1-bit units. for a mask rom version, use of an on-chip pull-up resistor can be specified by the mask option. input ? p60 ani0/cmpin0 p61 ani1/cmpref0 p62 to p66 input port 6. 7-bit input port. input ani2 to ani6 p80 to p87 i/o port 8. 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 2 (pu2). input s27 to s20 p90 to p93 i/o port 9. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 2 (pu2). input s19 to s16 chapter 2 pin functions 34 user?s manual u13952ej3v0ud (2) non-port pins (1/2) pin name i/o function after reset alternate function intp0 p24/ti0 intp1 p25/ti1 intp2 p26/to5 intp3 input external interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p27/cpt5 kr0 to kr5 input key return signal detection input p40 to p45 si input serial interface serial data input input p22/rxd so output serial interface serial data output input p21/txd sck i/o serial interface serial clock input/output input p20/asck asck input serial clock input for asynchronous serial interface input p20/sck rxd input serial data input for asynchronous serial interface input p22/si txd output serial data output for asynchronous serial interface input p21/so ti0 input external count clock input to 8-bit timer (tm00) input p24/intp0 ti1 input external count clock input to 8-bit timer (tm01) input p25/intp1 to2 output 8-bit timer (tm02) output input p23/cmptout0 to5 output 16-bit timer (tm50) output input p26/intp2 cpt5 input capture edge input input p27/intp3 cmptout0 output comparator output input p23/to2 cmpin0 input comparator input input p60/ani0 cmpref0 input comparator reference voltage input input p61/ani1 ani0 input a/d converter analog input input p60/cmpin0 ani1 p61/cmpref0 ani2 to ani6 p62 to p66 av ref ? a/d converter reference voltage ? ? av ss ? a/d converter ground potential ? ? av dd ? a/d converter analog power supply ? ? s0 to s15 output lcd controller/driver segment signal output output ? s16 to s19 input p93 to p90 s20 to s27 p87 to p80 com0 to com3 output lcd controller/driver common signal output output ? v lc0 to v lc2 ? lcd driving voltage ? ? bias ? supply voltage for lcd driving ? ? x1 input connecting crystal resonator for main system clock oscillation ? ? x2 ? ? ? xt1 input connecting crystal resonator for sub system clock oscillation ? ? xt2 ? ? ? reset input system reset input input ? chapter 2 pin functions user?s manual u13952ej3v0ud 35 (2) non-port pins (2/2) pin name i/o function after reset alternate function v dd0 ? positive power supply for ports ? ? v dd1 ? positive power supply for circuits other than ports ? ? v ss0 ? ground potential for ports ? ? v ss1 ? ground potential of circuits other than ports ? ? ic ? internally connected. connect directly to v ss0 or v ss1 . ? ? v pp ? sets flash memory programming mode. applies high voltage when a program is written or verified. ? ? chapter 2 pin functions 36 user?s manual u13952ej3v0ud 2.2 description of pin functions 2.2.1 p00 to p03 (port 0) these pins constitute a 4-bit i/o port and can be set to input or output port mode in 1-bit units by using port mode register 0 (pm0). when these pins are used as input port pins, an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (pu0). 2.2.2 p20 to p27 (port 2) these pins constitute an 8-bit i/o port. in addition to i/o port pins, these pins can also function as the data and clock i/o of the serial interface, external interrupt input, and timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode in this mode, p20 to p27 function as an 8-bit i/o port. these pins can be set to input or output mode in 1-bit units by using port mode register 2 (pm2). when used as input port pins, an on-chip pull-up resistor can be used by setting pull-up resistor option register 1 (pu1). (2) control mode in this mode, p20 to p27 function as the data i/o and the clock i/o of the serial interface, the external interrupt input, and timer i/o. (a) si, so these are the serial data i/o pins of the serial interface. (b) sck this is the serial clock i/o pin of the serial interface. (c) rxd, txd these are the serial data i/o pins of the asynchronous serial interface. (d) asck this is the serial clock input pin of the asynchronous serial interface. (e) ti0, ti1 these are external clock input pins for the 8-bit timer/event counter. (f) to2 this is the output pin of the 8-bit timer. (g) to5 this is the output pin of the 16-bit timer. (h) cpt5 this is the capture edge input pin. chapter 2 pin functions user?s manual u13952ej3v0ud 37 (i) intp0 to intp3 these are external interrupt input pins for which a valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (j) cmptout0 this is the comparator output pin. caution when using p20 to p27 as serial interface pins, the i/o mode and output latch must be set according to the function to be used. for details of the setting, refer to table 13-2. 2.2.3 p40 to p47 (port 4) these pins constitute an 8-bit i/o port. in addition to i/o port pins, these pins can also function as key return signal detection pins. the following operation modes can be specified in 1-bit units. (1) port mode in this mode, p40 to p47 function as an 8-bit i/o port. these pins can be set to input or output mode in 1-bit units by using port mode register 4 (pm4). when used as input port pins, an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (pu0). (2) control mode in this mode, the pins function as key return signal detection pins (kr0 to kr5). 2.2.4 p50 to p53 (port 5) these pins constitute a 4-bit n-channel open-drain i/o port. in the mask rom version, it is possible to specify that pull-up resistors be used, via a mask option. 2.2.5 p60 to p66 (port 6) these pins constitute a 7-bit input-only port. in addition to general-purpose input port pins, these pins can also function as a/d converter analog input pins and comparator input pins. (1) port mode in this port mode, p60 to p66 function as a 7-bit input-only port. (2) control mode in this mode, the pins can be used as a/d converter analog inputs and comparator inputs. (a) ani0 to ani6 these are the a/d converter analog input pins. (b) cmpin0 this is the comparator input pin. (c) cmpref0 this is the comparator reference voltage input pin. chapter 2 pin functions 38 user?s manual u13952ej3v0ud 2.2.6 p80 to p87 (port 8) these pins constitute an 8-bit i/o port. in addition to i/o port pins, these pins can also function as lcd controller/driver segment signal. the following operation modes can be specified in 1-bit units. (1) port mode in this port mode, p80 to p87 function as an 8-bit i/o port. these pins can be set to input or output mode in 1-bit units by using port mode register 8 (pm8). when used as an input port pins, an on-chip pull-up resistor can be used by setting pull-up resistor option register 2 (pu2). (2) control mode in this mode, p80 to p87 function as segment signal output pins (s20 to s27) for the lcd controller/driver. 2.2.7 p90 to p93 (port 9) these pins constitute a 4-bit i/o port. in addition to i/o port pins, these pins can also function as lcd controller/driver segment signal. the following operation modes can be specified in 1-bit units. (1) port mode in this mode, p90 to p93 function as a 4-bit i/o port. these pins can be set to input or output mode in 1-bit units by using port mode register 9 (pm9). when used as input port pins, an on-chip pull-up resistor can be used by setting pull-up resistor option register 2 (pu2). (2) control mode in this mode, p90 to p93 function as segment signal output pins (s16 to s19) for the lcd controller/driver. 2.2.8 s0 to s15 these pins are segment signal output pins for the lcd controller/driver. 2.2.9 com0 to com3 these pins are common signal output pins for the lcd controller/driver. 2.2.10 v lc0 to v lc2 these pins are power supply voltage pins to drive the lcd. 2.2.11 bias this pin supplies power to drive the lcd. 2.2.12 av ref this pin is the a/d converter reference voltage pin. connect it to v dd0 , v dd1 , v ss0 , or v ss1 when not using the a/d converter. 2.2.13 av dd this pin is the a/d converter analog circuit power supply pin. always keep it at the same potential as the v dd0 pin (even when the a/d converter is not used). chapter 2 pin functions user?s manual u13952ej3v0ud 39 2.2.14 av ss this pin is the a/d converter ground potential pin. always keep it at the same potential as the v ss0 pin (even when the a/d converter is not used). 2.2.15 reset this pin inputs an active-low system reset signal. 2.2.16 x1, x2 these pins are used to connect a crystal resonator for main system clock oscillation. to supply an external clock, input the clock to x1 and input the inverted signal to x2. 2.2.17 xt1, xt2 these pins are used to connect a crystal resonator for subsystem clock oscillation. to supply an external clock, input the clock to xt1 and input the inverted signal to xt2. 2.2.18 v dd0 , v dd1 v dd0 is the positive power supply pin for ports, while v dd1 is the positive power supply pin for other than ports. 2.2.19 v ss0 , v ss1 v ss0 is the ground potential pin for ports, while the v ss1 is the ground potential pin for other than ports. 2.2.20 v pp ( pd78f9418a only) a high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. handle the pins in either of the following ways. ? independently connect a 10 k ? pull-down resistor. ? switch this pin to be directly connected to the dedicated flash programmer in programming mode or to v ss0 or v ss1 in normal operation mode using a jumper on the board. if the wiring between the v pp pin and v ss0 or v ss1 pin is long, or external noise is superimposed on the v pp pin, the user program may not run correctly. chapter 2 pin functions 40 user?s manual u13952ej3v0ud 2.2.21 ic (mask rom version only) the ic (internally connected) pin is used to set the pd789407a and pd789417a subseries in the test mode before shipment. in the normal operation mode, directly connect this pin to the v ss0 or v ss1 pin with as short a wiring length as possible. if a potential difference is generated between the ic pin and v ss0 or v ss1 pin due to a long wiring length between these pin, or due to external noise superimposed on the ic pin, the user program may not run correctly. ? directly connect the ic pin to the v ss0 or v ss1 pin. v ss0 , v ss1 ic keep short chapter 2 pin functions user ? s manual u13952ej3v0ud 41 2.3 pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connection of unused pins are shown in table 2-1. for the i/o circuit configuration of each type, see figure 2-1. table 2-1. types of pin i/o circuits pin name i/o circuit type i/o recommended connection of unused pins p00 to p03 5-h p20/sck/asck p21/so/txd p22/si/rxd 8-c p23/cmptout0/to2 10-b input: independently connect to v dd0 , v dd1 , v ss0 , or v ss1 via a resistor. output: leave open. p24/intp0/ti0 p25/intp1/ti1 p26/intp2/to5 p27/intp3/cpt5 input: independently connect to v ss0 or v ss1 via a resistor. output: leave open. p40/kr0 to p45/kr5 8-c p46, p47 5-h input: independently connect to v dd0 , v dd1 , v ss0 , or v ss1 via a resistor. output: leave open. p50 to p53 (mask rom version) 13-u p50 to p53 ( pd78f9418a) 13-t i/o input: independently connect to v dd0 or v dd1 via a resistor. output: leave open. p60/ani0/cmpin0 p61/ani1/cmpref0 9-d p62/ani2 to p66/ani6 9-c input c onnect directly to v dd0 , v dd1 , v ss0 , or v ss1 . p80/s27 to p87/s20 p90/s19 to p93/s16 17-f i/o input: independently connect to v dd0 , v dd1 , v ss0 , or v ss1 via a resistor. output: leave open. s0 to s15 17-b com0 to com3 18-a output v lc0 to v lc2 leave open. bias leave open. however, independently connect to v ss0 or v ss1 via a resistor when none of v lc0 to v lc2 are used. av dd connect directly to v dd0 or v dd1 . av ref connect directly to v dd0 , v dd1 , v ss0 , or v ss1 . av ss ? connect directly to v ss0 or v ss1 . xt1 input connect directly to v ss0 or v ss1 . xt2 ? ? leave open. reset 2 input ? ic (mask rom version) connect directly to v ss0 or v ss1 . v pp ( pd78f9418a) ? ? independently connect to a 10 k ? pull-down resistor or connect directly to v ss0 or v ss1 . chapter 2 pin functions 42 user ? s manual u13952ej3v0ud figure 2-1. pin i/o circuits (1/2) type 2 type 9-d schmitt-triggered input with hysteresis characteristics in + ? p-ch n-ch in input enable comparator v ref av ss (threshold voltage) type 5-h type 10-b pull-up enable data output disable input enable v dd0 p-ch v dd0 p-ch in/out n-ch v ss0 pull-up enable data open drain output disable v dd0 p-ch v dd0 p-ch in/out n-ch v ss0 type 8-c type 13-t pull-up enable data output disable v dd0 p-ch v dd0 p-ch in/out n-ch v ss0 v ss0 data output disable in/out n-ch middle-voltage input buffer input enable type 9-c type 13-u in comparator + ? v ref (threshold voltage) av ss p-ch n-ch input enable v ss0 output data output disable in/out v dd0 n-ch middle-voltage input buffer input enable pull-up resistor (mask option) chapter 2 pin functions user ? s manual u13952ej3v0ud 43 figure 2-1. pin i/o circuits (2/2) type 17-b type 17-f p-ch v lc0 v lc1 n-ch p-ch n-ch v lc2 v ss1 seg data p-ch out n-ch type 18-a com data out p-ch v lc0 v lc1 n-ch v lc2 v ss1 p-ch n-ch p-ch n-ch n-ch p-ch p-ch v lc0 v lc1 v lc2 v ss1 seg data p-ch n-ch n-ch data output disable p-ch v dd0 v ss0 n-ch seg output disable input enable p-ch v dd0 pull-up enable in/out 44 user?s manual u13952ej3v0ud chapter 3 cpu architecture 3.1 memory space the pd789407a and pd789417a subseries can access 64 kb of memory space. figures 3-1 through 3-4 show the memory maps. figure 3-1. memory map ( pd789405a and pd789415a) special function registers 256 8 bits internal high-speed ram 512 8 bits ram space for lcd data 28 4 bits reserved reserved internal rom 12288 8 bits ffffh ff00h feffh fd00h fcffh fa00h f9ffh 0000h program memory space data memory space 2fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0024h 0023h vector table area fa1ch fa1bh 3000h 2fffh chapter 3 cpu architecture user ? s manual u13952ej3v0ud 45 figure 3-2. memory map ( pd789406a and pd789416a) special function registers 256 8 bits internal high-speed ram 512 8 bits internal rom 16384 8 bits ffffh ff00h feffh 0000h program memory space data memory space 3fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0024h 0023h vector table area ram space for lcd data 28 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa1ch fa1bh 4000h 3fffh chapter 3 cpu architecture 46 user ? s manual u13952ej3v0ud figure 3-3. memory map ( pd789407a and pd789417a) special function registers 256 8 bits internal high-speed ram 512 8 bits internal rom 24576 8 bits ffffh ff00h feffh 0000h program memory space data memory space 5fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0024h 0023h vector table area ram space for lcd data 28 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa1ch fa1bh 6000h 5fffh chapter 3 cpu architecture user ? s manual u13952ej3v0ud 47 figure 3-4. memory map ( pd78f9418a) special function registers 256 8 bits internal high-speed ram 512 8 bits flash memory 32768 8 bits ffffh ff00h feffh 0000h program memory space data memory space 7fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0024h 0023h vector table area ram space for lcd data 28 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa1ch fa1bh 8000h 7fffh chapter 3 cpu architecture 48 user ? s manual u13952ej3v0ud 3.1.1 internal program memory space the internal program memory space stores programs and table data. this space is usually addressed by the program counter (pc). the products in the pd789407a and pd789417a subseries contain the following internal rom (or flash memory) capacities. table 3-1. internal rom capacity part number internal rom structure capacity pd789405a, 789415a mask rom 12288 8 bits pd789406a, 789416a 16384 8 bits pd789407a, 789417a 24576 8 bits pd78f9418a flash memory 32768 8 bits the following areas are allocated to the internal program memory space. (1) vector table area the 36-byte area of addresses 0000h to 0023h is reserved as a vector table area. this area stores program start addresses to be used when branching by reset input or interrupt request generation. of a 16-bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address. table 3-2. vector table vector table address interrupt request vector table address interrupt request 0000h reset input 0014h intwti 0004h intwdt 0016h inttm00 0006h intp0 0018h inttm01 0008h intp1 001ah inttm02 000ah intp2 001ch inttm50 000ch intp3 001eh intkr00 000eh intsr00/intcsi00 0020h intad0 0010h intst00 0022h intcmp0 0012h intwt (2) callt instruction table area the subroutine entry address of a 1-byte call instruction (callt) can be stored in the 64-byte area of addresses 0040h to 007fh. chapter 3 cpu architecture user ? s manual u13952ej3v0ud 49 3.1.2 internal data memory space the pd789407a and pd789417a subseries products incorporate the following ram: (1) internal high-speed ram an internal high-speed ram is allocated to the area between fd00h and feffh. the internal high-speed ram is also used as a stack. (2) lcd data ram an lcd data ram is allocated to the area between fa00h and fa1bh. the lcd display ram can also be used as ordinary ram. 3.1.3 special function register (sfr) area special function registers (sfrs) of on-chip peripheral hardware are allocated to the area of ff00h to ffffh (see table 3-3 ). chapter 3 cpu architecture 50 user ? s manual u13952ej3v0ud 3.1.4 data memory addressing the pd789407a and pd789417a subseries are provided with a variety of addressing modes to make memory manipulation as efficient as possible. in the area that holds data memory (fd00h to ffffh) especially, specific modes of addressing that correspond to the particular function of an area, such as the special function registers (sfr) or general-purpose registers, are available. figures 3-5 through 3-8 show the data memory addressing modes. figure 3-5. data memory addressing ( pd789405a and pd789415a) special function registers (sfr) 256 8 bits internal high-speed ram 512 8 bits internal rom 12288 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing ram space for lcd data 28 4 bits reserved reserved fd00h fcffh fa00h f9ffh 3000h 2fffh fa1ch fa1bh chapter 3 cpu architecture user ? s manual u13952ej3v0ud 51 figure 3-6. data memory addressing ( pd789406a and pd789416a) special function registers (sfr) 256 8 bits internal high-speed ram 512 8 bits internal rom 16384 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing ram space for lcd data 28 4 bits reserved reserved fd00h fcffh fa00h f9ffh 4000h 3fffh fa1ch fa1bh chapter 3 cpu architecture 52 user ? s manual u13952ej3v0ud figure 3-7. data memory addressing ( pd789407a and pd789417a) special function registers (sfr) 256 8 bits internal high-speed ram 512 8 bits internal rom 24576 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing ram space for lcd data 28 4 bits reserved reserved fd00h fcffh fa00h f9ffh 6000h 5fffh fa1ch fa1bh chapter 3 cpu architecture user ? s manual u13952ej3v0ud 53 figure 3-8. data memory addressing ( pd78f9418a) special function registers (sfr) 256 8 bits internal high-speed ram 512 8 bits flash memory 32768 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing ram space for lcd data 28 4 bits reserved reserved fd00h fcffh fa00h f9ffh 8000h 7fffh fa1ch fa1bh chapter 3 cpu architecture 54 user?s manual u13952ej3v0ud 3.2 processor registers the pd789407a and pd789417a subseries are provided with the following on-chip processor registers. 3.2.1 control registers the control registers contains special functions to control the program sequence statuses and stack memory. a program counter, a program status word, and a stack pointer constitute the control registers. (1) program counter (pc) the program counter is a 16-bit register that holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data or register contents are set. reset input sets the program counter to the reset vector table values at addresses 0000h and 0001h. figure 3-9. program counter configuration 0 15 pc14 pc15 pc pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically restored upon execution of the reti and pop psw instructions. reset input sets the psw to 02h. figure 3-10. program status word configuration 70 ie z0ac001cy chapter 3 cpu architecture user ? s manual u13952ej3v0ud 55 (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledgment operations of the cpu. when 0, ie is set to the interrupt disable status (di), and all interrupt requests other than non-maskable interrupts are disabled. when 1, ie is set to the interrupt enable status (ei). at this time, interrupt request acknowledgment is controlled by an interrupt mask flag corresponding to the interrupt source. ie is reset (0) upon di instruction execution or interrupt acknowledgment and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set (1). it is reset (0) in all other cases. (c) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (d) carry flag (cy) this flag stores an overflow or underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. chapter 3 cpu architecture 56 user ? s manual u13952ej3v0ud (3) stack pointer (sp) this is a 16-bit register used to hold the start address of the memory stack area. only the internal high- speed ram area can be set as the stack area. figure 3-11. stack pointer configuration 0 15 sp14 sp15 sp sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. each stack operation saves/restores data as shown in figures 3-12 and 3-13. caution since reset input makes the sp contents undefined, be sure to initialize the sp before instruction execution. figure 3-12. data saved to stack memory interrupt psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower register pairs sp sp _ 2 sp _ 2 call, callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 higher register pairs figure 3-13. data restored from stack memory reti instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower register pairs ret instruction pop rp instruction sp pc7 to pc0 higher register pairs sp + 1 sp sp + 2 sp sp + 1 sp sp + 2 sp sp + 1 sp + 2 sp sp + 3 chapter 3 cpu architecture user ? s manual u13952ej3v0ud 57 3.2.2 general-purpose registers the general-purpose registers consist of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register, and two 8-bit registers can be used in pairs as a 16-bit register (ax, bc, de, and hl). general-purpose registers can be described in terms of functional names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). figure 3-14. general-purpose register configuration (a) absolute names r0 15 0 7 0 16-bit processing 8-bit processing rp3 rp2 rp1 rp0 r1 r2 r3 r4 r5 r6 r7 (b) functional names x 15 0 7 0 16-bit processing 8-bit processing hl de bc ax a c b e d l h chapter 3 cpu architecture 58 user ? s manual u13952ej3v0ud 3.2.3 special function registers (sfr) unlike a general-purpose register, each special function register has a special function. sfrs are allocated in the 256-byte area ff00h to ffffh. a special function register can be manipulated, like a general-purpose register, using operation, transfer, and bit manipulation instructions. the manipulatable bit unit (1, 8, or 16) differs depending on the special function register type. each manipulation bit unit can be specified as follows. 1-bit manipulation describes a symbol reserved by assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified by an address. 8-bit manipulation describes a symbol reserved by assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified by an address. 16-bit manipulation describes a symbol reserved by assembler for the 16-bit manipulation instruction operand. when addressing an address, describe an even address. table 3-3 lists the special function registers. the meanings of the symbols in this table are as follows: symbol indicates the address of the special function register. the symbols shown in this column are reserved words in the assembler, and have been defined in the header file named ? sfrbit.h ? in the c compiler. therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used. r/w indicates whether the special function register in question can be read or written. r/w: read/write r: read only w: write only manipulatable bit unit indicates the bit units (1, 8, 16) in which the special function register in question can be manipulated. after reset indicates the status of the special function register when the reset signal is input. chapter 3 cpu architecture user ? s manual u13952ej3v0ud 59 table 3-3. special function register list (1/2) address special function register (sfr) name symbol r/w manipulatable bit unit after reset 1 bit 8 bits 16 bits ff00h port 0 p0 r/w ? ? 00h ff02h port 2 p2 ? ? ff04h port 4 p4 ? ? ff05h port 5 p5 ? ? ff06h port 6 p6 r ? ? ff08h port 8 p8 r/w ? ? ff09h port 9 p9 ? ? ff10h transmit shift register 00 txs00 sio00 w ? ? ffh receive buffer register 00 rxb00 r ? ? undefined ff14h a/d conversion result register 0 adcr0 ? note 1 note 2 ff15h ff16h 16-bit compare register 50 cr50l w ?? notes 2, 3 ffffh ff17h cr50h cr50 ff18h 16-bit timer counter 50 tm50l ?? notes 2, 3 0000h ff19h tm50h tm50 ff1ah 16-bit capture register 50 tcp50l ?? notes 2, 3 undefined ff1bh tcp50h tcp50 r ff20h port mode register 0 pm0 r/w ? ? ffh ff22h port mode register 2 pm2 ? ? ff24h port mode register 4 pm4 ? ? ff25h port mode register 5 pm5 ? ? ff28h port mode register 8 pm8 ? ? ff29h port mode register 9 pm9 ? ? ff42h timer clock selection register 2 tcl2 ? ? 00h ff48h 16-bit timer mode control register 50 tmc50 ? ? ff4ah watch timer mode control register wtm ? ? ff4eh comparator mode register 0 cmprm0 ? ? notes 1. if the a/d conversion result register is used for the 8-bit a/d converter ( pd789407a subseries), it can be accessed only in 8-bit units. in this case, it is considered to have been mapped at address ff15h. if the register is used for the 10-bit a/d converter ( pd789417a subseries), it can be accessed only in 16-bit units. if the pd78f9418a is used as the flash memory version of the pd789405a, pd789406a, or pd789407a, 8-bit access is also possible, provided that the object file has been assembled using the pd789405a, pd789406a, or pd789407a. 2. 16-bit access is possible only in short direct addressing. 3. although cr50, tm50, and tcp50 are 16-bit access dedicated registers, an 8-bit access is also possible. when performing an 8-bit access, use direct addressing. chapter 3 cpu architecture 60 user ? s manual u13952ej3v0ud table 3-3. special function register list (2/2) address special function register (sfr) name symbol r/w manipulatable bit unit after reset 1 bit 8 bits 16 bits ff50h 8-bit compare register 00 cr00 w ? ? undefined ff51h 8-bit timer counter 00 tm00 r ? ? 00h ff53h 8-bit timer mode control register 00 tmc00 r/w ? ? ff54h 8-bit compare register 01 cr01 w ? ? undefined ff55h 8-bit timer counter 01 tm01 r ? ? 00h ff57h 8-bit timer mode control register 01 tmc01 r/w ? ? ff58h 8-bit compare register 02 cr02 w ? ? undefined ff59h 8-bit timer counter 02 tm02 r ? ? ff5bh 8-bit timer mode control register 02 tmc02 r/w ? ? ff70h asynchronous serial interface mode register 00 asim00 ? ? ff71h asynchronous serial interface status register 00 asis00 r ? ? ff72h serial operation mode register 00 csim00 r/w ? ? ff73h baud rate generator control register 00 brgc00 ? ? ff80h a/d converter mode register 0 adm0 ? ? ff84h a/d input selection register 0 ads0 ? ? ffb0h lcd display mode register 0 lcdm0 ? ? ffb1h lcd port selector 0 lps0 ? ? ffb2h lcd clock control register 0 lcdc0 ? ? ffe0h interrupt request flag register 0 if0 ? ? ffe1h interrupt request flag register 1 if1 ? ? 00h ffe4h interrupt mask flag register 0 mk0 ? ? ffh ffe5h interrupt mask flag register 1 mk1 ? ? ffech external interrupt mode register 0 intm0 ? ? 00h ffedh external interrupt mode register 1 intm1 ? ? fff0h suboscillation mode register sckm ? ? fff2h subclock control register css ? ? fff3h pull-up resistor option register 1 pu1 ? ? fff4h pull-up resistor option register 2 pu2 ? ? fff5h key return mode register 00 krm00 ? ? fff7h pull-up resistor option register 0 pu0 ? ? fff9h watchdog timer mode register wdtm ? ? fffah oscillation stabilization time selection register osts ? ? 04h fffbh processor clock control register pcc ? ? 02h chapter 3 cpu architecture user ? s manual u13952ej3v0ud 61 3.3 instruction address addressing an instruction address is determined by program counter (pc) contents. pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing (for details of each instruction, refer to the 78k/0s series instructions user?s manual (u11047e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed two ? s complement data ( ? 128 to +127) and bit 7 becomes a sign bit. this means that information is relatively branched to a location between ? 128 and +127, from the start address of the next instruction when relative addressing is used. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 15 0 pc 15 0 s 15 0 pc + 876 jdisp8 when s = 0, indicates all bits 0. ... pc is the start address of the next instruction of a br instruction. when s = 1, indicates all bits 1. chapter 3 cpu architecture 62 user ? s manual u13952ej3v0ud 3.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 instruction is executed. the call !addr16 and br !addr16 instructions can be branched to any location in the memory space. [illustration] in case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr. chapter 3 cpu architecture user ? s manual u13952ej3v0ud 63 3.3.3 table indirect addressing [function] the table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (pc) and branched. this function is carried out when the callt [addr5] instruction is executed. the instruction enables a branch to any location in the memory space by referring to the addresses stored in the memory table at 40h to 7fh. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 0 01 765 10 ta 4 ? 0 instruction code 3.3.4 register addressing [function] the register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87 chapter 3 cpu architecture 64 user ? s manual u13952ej3v0ud 3.4 operand address addressing the following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 direct addressing [function] the memory indicated with immediate data in an instruction word is directly addressed. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !fe00h; when setting !addr16 to fe00h instruction code 00101001 opcode 00000000 11111110 00h feh [illustration] 70 opcode addr16 (low) addr16 (high) memory ? ? ? ? ? chapter 3 cpu architecture user ? s manual u13952ej3v0ud 65 3.4.2 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. the fixed space is the 256-byte space fe20h to ff1fh where the addressing is applied. an internal high- speed ram and special function registers (sfr) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addressing is applied is a part of the whole sfr area. ports that are frequently accessed in a program and a compare register of the timer/event counter are mapped in this area, and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. see [illustration] below. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh immediate data (even address only) [description example] mov fe30h, #50h; when setting saddr to fe30h and the immediate data to 50h instruction code 1 1110101 00110000 01010000 opcode 30h (saddr-offset) 50h (immediate data) [illustration] 15 0 short direct memory effective address 1 111111 8 0 7 opcode saddr-offset when 8-bit immediate data is 20h to ffh, = 0. when 8-bit immediate data is 00h to 1fh, = 1. chapter 3 cpu architecture 66 user ? s manual u13952ej3v0ud 3.4.3 special function register (sfr) addressing [function] a memory-mapped special function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfrs mapped at ff00h to ff1fh can be accessed using short direct addressing. [operand format] identifier description sfr special function register name [description example] mov pm0, a; when selecting pm0 for sfr instruction code 11100111 00100000 [illustration] 15 0 sfr effective address 1 111111 87 0 7 opcode sfr-offset 1 chapter 3 cpu architecture user ? s manual u13952ej3v0ud 67 3.4.4 register addressing [function] in the register addressing mode, general-purpose registers are accessed as operands. the general-purpose register to be accessed is specified by the register specification code or functional name in the instruction code. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl r and rp can be described using absolute names (r0 to r7 and rp0 to rp3) as well as functional names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting the c register for r instruction code 0 0 0 0 1 0 1 0 00100101 register specification code incw de; when selecting the de register pair for rp instruction code 1 0 0 0 1000 register specification code chapter 3 cpu architecture 68 user ? s manual u13952ej3v0ud 3.4.5 register indirect addressing [function] in the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. the register pair to be accessed is specified by the register pair specification code in an instruction code. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting register pair [de] instruction code 0 0 1 01011 [illustration] 15 0 8 d 7 e 0 7 7 0 a de addressed memory contents are transferred. memory address specified with register pair de. chapter 3 cpu architecture user ? s manual u13952ej3v0ud 69 3.4.6 based addressing [function] 8-bit immediate data is added to the contents of the base register, that is, the hl register pair, and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl+byte] [description example] mov a, [hl+10h]; when setting byte to 10h instruction code 0 0 1 01101 00010000 3.4.7 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request. stack addressing can only be used to access the internal high-speed ram area. [description example] in the case of push de instruction code 10101010 70 user?s manual u13952ej3v0ud chapter 4 port functions 4.1 function of port the pd789407a and pd789417a subseries are provided with the ports shown in figure 4-1, enabling various methods of control. numerous other functions are provided that can be used in addition to the digital i/o port function. for more information on these additional functions, see chapter 2 pin functions . figure 4-1. port types p50 p53 p00 p03 p60 p66 p80 p87 p40 p47 p90 p93 port 5 port 6 ? ? ? ? ? ? ? ? ? ? port 9 ? ? ? ? ? ? ? ? ? ? ? ? ? ? port 8 ? ? ? ? ? ? ? ? ? ? ? port 4 ? ? ? ? ? ? ? ? ? ? ? p20 p27 port 2 port 0 ? ? ? ? ? ? ? ? ? ? ? chapter 4 port functions user ? s manual u13952ej3v0ud 71 table 4-1. port functions pin name i/o function after reset alternate function p00 to p03 i/o port 0. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 0 (pu0). input ? p20 sck/asck p21 so/txd p22 si/rxd p23 cmptout0/to2 p24 intp0/ti0 p25 intp1/ti1 p26 intp2/to5 p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 1 (pu1). input intp3/cpt5 p40 to p45 input kr0 to kr5 p46, p47 i/o port 4. 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 0 (pu0). ? p50 to p53 i/o port 5. 4-bit n-ch open-drain i/o port. input/output can be specified in 1-bit units. for a mask rom version, use of an on-chip pull-up resistor can be specified by the mask option. input ? p60 input ani0/cmpin0 p61 ani1/cmpref0 p62 to p66 input port 6. 7-bit input port. ani2 to ani6 p80 to p87 i/o port 8. 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 2 (pu2). input s27 to s20 p90 to p93 i/o port 9. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 2 (pu2). input s19 to s16 chapter 4 port functions 72 user ? s manual u13952ej3v0ud 4.2 configuration of ports the ports consist of the following hardware. table 4-2. configuration of port item configuration control registers port mode registers (pmm: m = 0, 2, 4, 5, 8, 9) pull-up resistor option registers (pum: m = 0 to 2) ports total: 43 (input: 7, i/o: 36) pull-up resistors ? mask rom version total: 36 (software control: 32, mask option control: 4) ? flash memory version total: 32 (software control only) 4.2.1 port 0 this is a 4-bit i/o port with an output latch. port 0 can be specified as input or output in 1-bit units by using port mode register 0 (pm0). when the p00 to p03 pins are used as input port pins, on-chip pull-up resistors can be connected in 4-bit units by setting pull-up resistor option register 0 (pu0). port 0 is set to input mode when the reset signal is input. figure 4-2 shows a block diagram of port 0. figure 4-2. block diagram of p00 to p03 internal bus wr pu0 rd wr port wr pm pu00 output latch (p00 to p03) pm00 to pm03 v dd0 p-ch p00 to p03 selector pu0: pull-up resistor option register 0 pm: port mode register rd: port 0 read signal wr: port 0 write signal chapter 4 port functions user ? s manual u13952ej3v0ud 73 4.2.2 port 2 this is an 8-bit i/o port with an output latch. port 2 can be specified as input or output in 1-bit units by using port mode register 2 (pm2). when using the p20 to p27 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by setting pull-up resistor option register 1 (pu1). port 2 is also used as a data i/o and clock i/o to and from the serial interface, timer i/o, and external interrupt. port 2 is set to input mode when the reset signal is input. figures 4-3 through 4-7 show block diagrams of port 2. caution when using the pins of port 2 for the serial interface, the i/o or output latch must be set according to the function to be used. for how to set the latches, see table 13-2 operation mode settings of serial interface 00. figure 4-3. block diagram of p20 internal bus v dd0 p-ch p20/asck/ sck wr pu1 rd wr port wr pm pu120 alternate function output latch (p20) pm20 alternate function selector pu1: pull-up resistor option register 1 pm: port mode register rd: port 2 read signal wr: port 2 write signal chapter 4 port functions 74 user ? s manual u13952ej3v0ud figure 4-4. block diagram of p21 internal bus v dd0 p-ch p21/txd/ so wr pu1 rd wr port wr pm pu121 output latch (p21) pm21 alternate function selector pu1: pull-up resistor option register 1 pm: port mode register rd: port 2 read signal wr: port 2 write signal chapter 4 port functions user ? s manual u13952ej3v0ud 75 figure 4-5. block diagram of p22 and p24 internal bus v dd0 p-ch p22/rxd/si p24/intp0/ti0 wr pu1 rd wr port wr pm pu122, pu124 alternate function output latch (p22, p24) pm22, pm24 selector pu1: pull-up resistor option register 1 pm: port mode register rd: port 2 read signal wr: port 2 write signal chapter 4 port functions 76 user ? s manual u13952ej3v0ud figure 4-6. block diagram of p23 internal bus rd wr pu1 opdr pm23 alternate function alternate function output latch (p23) pu123 p-ch wr port wr pm v dd0 v dd0 p-ch n-ch p23/to2 /cmptout0 selector opdr: bit 1 of comparator mode register 0, selection of n-ch open-drain output pu1: pull-up resistor option register 1 pm: port mode register rd: port 2 read signal wr: port 2 write signal chapter 4 port functions user ? s manual u13952ej3v0ud 77 figure 4-7. block diagram of p25 to p27 internal bus v dd0 p25/intp1/ti1 p26/intp2/to5 p27/intp3/cpt5 wr pu1 rd wr port wr pm pu125 to pu127 alternate function alternate function output latch (p25 to p27) pm25 to pm27 selector p-ch pu1: pull-up resistor option register 1 pm: port mode register rd: port 2 read signal wr: port 2 write signal chapter 4 port functions 78 user ? s manual u13952ej3v0ud 4.2.3 port 4 this is an 8-bit i/o port with an output latch. port 4 can be specified as input or output in 1-bit units by using port mode register 4 (pm4). when using the p40 to p47 pins as input port pins, on-chip pull-up resistors can be connected in 8-bit units by setting pull-up resistor option register 0 (pu0). port 4 is also used as a key return input. port 4 is set to input mode when the reset signal is input. figures 4-8 and 4-9 show block diagrams of port 4. caution when using the pins of port 4 as the key return, the key return mode register must be set according to the function to be used. for how to set the registers, see 15.3 (6) key return mode register 00 (krm00). figure 4-8. block diagram of p40 to p45 wr krm internal bus v dd0 p40/kr0 to p45/kr5 wr pu0 rd wr port wr pm pu04 alternate function output latch (p40 to p45) pm40 to pm45 krm000 to krm005 selector p-ch krm00: key return mode register 00 pu0: pull-up resistor option register 0 pm: port mode register rd: port 4 read signal wr: port 4 write signal chapter 4 port functions user ? s manual u13952ej3v0ud 79 figure 4-9. block diagram of p46 and p47 internal bus wr pu0 rd wr port wr pm pu04 output latch (p46, p47) pm46, pm47 v dd0 p-ch p46, p47 selector pu0: pull-up resistor option register 0 pm: port mode register rd: port 4 read signal wr: port 4 write signal chapter 4 port functions 80 user?s manual u13952ej3v0ud 4.2.4 port 5 this is a 4-bit n-ch open-drain i/o port with an output latch. port 5 can be specified as input or output in 1-bit units by using port mode register 5 (pm5). for a mask rom version, whether a pull-up resistor is to be incorporated can be specified by a mask option. port 5 is set to input mode when the reset signal is input. figure 4-10 shows a block diagram of port 5. figure 4-10. block diagram of p50 to p53 internal bus selector rd pm50 to pm53 p50 to p53 n-ch wr port output latch (p50 to p53) wr pm v dd0 mask option resistor mask rom version only. for the flash memory version, a pull-up resistor is not incorporated. pm: port mode register rd: port 5 read signal wr: port 5 write signal chapter 4 port functions user ? s manual u13952ej3v0ud 81 4.2.5 port 6 this is a 7-bit input port. port 6 is also used as an analog input to the a/d converter or comparator input. port 6 is set to input mode when the reset signal is input. figures 4-11 and 4-12 show block diagrams of port 6. figure 4-11. block diagram of p60 and p61 internal bus v ref rd a/d converter p60/ani0/cmpin0 p61/ani1/cmpref0 comparator + ? chapter 4 port functions 82 user ? s manual u13952ej3v0ud figure 4-12. block diagram of p62 to p66 internal bus v ref rd + ? a/d converter p62/ani2 to p66/ani6 chapter 4 port functions user ? s manual u13952ej3v0ud 83 4.2.6 port 8 this is an 8-bit i/o port with an output latch. port 8 can be specified as input or output in 1-bit units by using port mode register 8 (pm8). when using the p80 to p87 pins as input port pins, internal pull-up resistors can be connected in 2-bit units by using pull-up resistor option register 2 (pu2). port 8 is also used to output segment signals for the lcd controller/driver. port 8 is set to input mode when the reset signal is input. figure 4-13 shows a block diagram of port 8. figure 4-13. block diagram of p80 to p87 internal bus wr pu2 v dd0 p-ch wr port wr pm output latch (p8m) pm8m lps0 segment output wr lps rd pu28n p80/s27 to p87/s20 selector pu2: pull-up resistor option register 2 pm: port mode register rd: port 8 read signal wr: port 8 write signal lps0: lcd port selector 0 n = 0, 2, 4, 6, m = 0 to 7 chapter 4 port functions 84 user ? s manual u13952ej3v0ud 4.2.7 port 9 this is a 4-bit i/o port with an output latch. port 9 can be specified as input or output in 1-bit units by using port mode register 9 (pm9). when using the p90 to p93 pins as input port pins, on-chip pull-up resistors can be connected in 2-bit units by using pull-up resistor option register 2 (pu2). port 9 is also used to output segment signals for the lcd controller/driver. port 9 is set to input mode when the reset signal is input. figure 4-14 shows a block diagram of port 9. figure 4-14. block diagram of p90 to p93 internal bus wr pu2 v dd0 p-ch wr port wr pm output latch (p9m) pm9m lps0 segment output wr lps rd pu29n p90/s19 to p93/s16 selector pu2: pull-up resistor option register 2 pm: port mode register rd: port 9 read signal wr: port 9 write signal lps0: lcd port selector 0 n = 0, 2, m = 0 to 3 chapter 4 port functions user ? s manual u13952ej3v0ud 85 4.3 registers controlling ports the following two registers control the ports. ? port mode registers (pm0, pm2, pm4, pm5, pm8, and pm9) ? pull-up resistor option registers (pu0 to pu2) (1) port mode registers (pm0, pm2, pm4, pm5, pm8, and pm9) these registers are used to set port input/output in 1-bit units. the port mode registers are independently set using a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to ffh. when port pins are used as alternate-function pins, set the port mode register and output latch according to table 4-3. caution as port 2 has an alternate function as the external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. when the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. table 4-3. port mode register and output latch settings when using alternate functions alternate function pin name name i/o pmxx pxx cmptout0 output 0 0 p23 to2 output 0 0 intp0 input 1 x p24 ti0 input 1 x intp1 input 1 x p25 ti1 input 1 x intp2 input 1 x p26 to5 output 0 0 intp3 input 1 x p27 cpt5 input 1 x p40 to p45 note kr0 to kr5 input 1 x p80 to p87 s27 to s20 output 0 0 p90 to p93 s19 to s16 output 0 0 note set key return mode register 00 (krm00) to 1 when using the alternate function (see 15.3 (6) key return mode register 00 (krm00) ). caution when port 2 is used for the serial interface, the i/o or output latch must be set according to the function used. for the setting method, see table 13-2 operation mode settings of serial interface 00. remark x: don ? t care pmxx: port mode register pxx: port output latch chapter 4 port functions 86 user ? s manual u13952ej3v0ud figure 4-15. format of port mode register pmmn 0 output mode (output buffer on) input mode (output buffer off) 1 1 pm27 pm87 1 1 pm26 pm86 1 1 pm25 pm85 1 1 pm24 pm84 1 pm03 pm23 pm83 pm93 pm02 pm22 pm82 pm92 pm01 pm21 pm81 pm91 pm00 pm20 pm80 pm90 pm0 pm2 pm8 pm9 7 symbol address after reset 6543210 r/w ff20h ff22h ff28h ff29h ffh ffh ffh ffh r/w r/w r/w r/w pm47 1 pm46 1 pm45 1 pm44 1 pm43 pm53 pm42 pm52 pm41 pm51 pm40 pm50 pm4 pm5 ff24h ff25h ffh ffh r/w r/w pmn pin i/o mode selection m = 0, 5, 9: n = 0 to 3 m = 2, 4, 8: n = 0 to 7 (2) pull-up resistor option registers (pu0 to pu2) the pull-up resistor option registers (pu0 to pu2) set whether an on-chip pull-up resistor is used on each port. on a port specified by pu0 to pu2 to use an on-chip pull-up resistor, the pull-up resistor can be internally used only for the bits set in the input mode. no on-chip pull-up resistors can be used for the bits set in the output mode regardless of the setting of pu0 to pu2. this also applies when using the pins for alternate functions. pu0 to pu2 are set using a 1-bit or 8-bit memory manipulation instruction. reset input sets pu0 to pu2 to 00h. figure 4-16. format of pull-up resistor option register 0 pm on-chip pull-up resistor selection note (m = 0 or 4) 0 0 0 pu04 0 0 0 pu00 pu0 address after reset r/w fff7h 00h r/w 765<4>321<0> pu0m 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol note pu0 selects whether on-chip pull-up resistors are to be used in 8-bit units, except for port 0, for which on- chip pull-up resistors can be used only for four bits (p00 to p03). caution bits 1, 2, 3, 5, 6, and 7 must be fixed to 0. chapter 4 port functions user ? s manual u13952ej3v0ud 87 figure 4-17. format of pull-up resistor option register 1 p2 on-chip pull-up resistor selection note (m = 0 to 7) pu127 pu126 pu125 pu124 pu123 pu122 pu121 pu120 pu1 address after reset r/w fff3h 00h r/w <7> <6> <5> <4> <3> <2> <1> <0> pu12m 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol note pu1 selects whether on-chip pull-up resistors are to be used in 1-bit units. figure 4-18. format of pull-up resistor option register 2 pm on-chip pull-up resistor selection note (m = 8 or 9; n = 0, 2, 4, or 6) 00 pu292 pu290 pu286 pu284 pu282 pu280 pu2 address after reset r/w fff4h 00h r/w 7 6 <5> <4> <3> <2> <1> <0> pu2mn 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol note pu2 selects whether on-chip pull-up resistors are to be used in 2-bit units (bit n and bit n+1). caution bits 6 and 7 must be fixed to 0. chapter 4 port functions 88 user ? s manual u13952ej3v0ud 4.4 operation of ports the operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 writing to i/o port (1) in output mode a value can be written to the output latch of a port by using a transfer instruction. the contents of the output latch can be output from the pins of the port. once data is written to the output latch, it is retained until new data is written to the output latch. (2) in input mode a value can be written to the output latch by using a transfer instruction. however, the status of the port pin is not changed because the output buffer is off. once data is written to the output latch, it is retained until new data is written to the output latch. caution a 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of an i/o port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 4.4.2 reading from i/o port (1) in output mode the contents of the output latch can be read by using a transfer instruction. the contents of the output latch are not changed. (2) in input mode the status of a pin can be read by using a transfer instruction. the contents of the output latch are not changed. 4.4.3 arithmetic operation of i/o port (1) in output mode an arithmetic operation can be performed on the contents of the output latch. the result of the operation is written to the output latch. the contents of the output latch are output from the port pins. once data is written to the output latch, it is retained until new data is written to the output latch. (2) in input mode the contents of the output latch become undefined. however, the status of the pin is not changed because the output buffer is off. caution a 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of an i/o port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. user?s manual u13952ej3v0ud 89 chapter 5 clock generator 5.1 functions of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators are used. ? ? ? ? main system clock oscillator this circuit oscillates at 1.0 to 5.0 mhz. oscillation can be stopped by executing the stop instruction or setting the processor clock control register (pcc). ? ? ? ? subsystem clock oscillator this circuit oscillates at 32.768 khz. oscillation can be stopped by the suboscillation mode register (sckm). 5.2 configuration of clock generator the clock generator consists of the following hardware. table 5-1. configuration of clock generator item configuration control registers processor clock control register (pcc) suboscillation mode register (sckm) subclock control register (css) oscillators main system clock oscillator subsystem clock oscillator chapter 5 clock generator 90 user?s manual u13952ej3v0ud figure 5-1. block diagram of clock generator f xt f x prescaler f x 2 2 f xt 2 1/2 prescaler watch timer lcd controller/driver clock to peripheral hardware cpu clock (f cpu ) standby controller wait controller selector stop mcc pcc1 cls css0 internal bus suboscillation mode register (sckm) frc scc internal bus subclock control register (css) processor clock control register (pcc) subsystem clock oscillator x1 x2 xt1 xt2 main system clock oscillator chapter 5 clock generator user?s manual u13952ej3v0ud 91 5.3 registers controlling clock generator the clock generator is controlled by the following registers. ? processor clock control register (pcc) ? suboscillation mode register (sckm) ? subclock control register (css) (1) processor clock control register (pcc) pcc selects the cpu clock and sets the division ratio. pcc is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets pcc to 02h. figure 5-2. format of processor clock control register 0.4 s 1.6 s 122 s control of main system clock oscillator operation mcc00000 pcc1 0 pcc symbol address after reset r/w fffbh 02h r/w 76543210 mcc 0 1 operation enabled operation disabled selection of cpu clock (f cpu ) note css0 0 0 1 1 pcc1 0 1 0 1 f x f x /2 2 f xt /2 minimum instruction execution time: 2/f cpu f x = 5.0 mhz or f xt = 32.768 khz operation note the cpu clock is selected according to a combination of the pcc1 flag in the processor clock control register (pcc) and the css0 flag in the subclock control register (css). see 5.3 (3) subclock control register (css) . cautions 1. bits 0 and 2 to 6 must be fixed to 0. 2. the mcc bit can be set only when the subsystem clock has been selected as the cpu clock. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency chapter 5 clock generator 92 user ? s manual u13952ej3v0ud (2) suboscillation mode register (sckm) sckm selects whether a feedback resistor is used for the subsystem clock, and controls the oscillation of the clock. sckm is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets sckm to 00h. figure 5-3. format of suboscillation mode register feedback resistor selection note 000000frcscc sckm symbol address after reset r/w fff0h 00h r/w 76543210 frc 0 1 on-chip feedback resistor used on-chip feedback resistor not used control of subsystem clock oscillator operation scc 0 1 operation enabled operation disabled note the feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid point of the supply voltage. only when the subclock is not used, the power consumption in stop mode can be further reduced by setting frc = 1. cautions 1. bits 2 to 7 must be fixed to 0. 2. do not set the scc bit when an external clock pulse is input, because the xt2 pin is pulled up to v dd0 or v dd1 . chapter 5 clock generator user ? s manual u13952ej3v0ud 93 (3) subclock control register (css) css specifies whether the main system or subsystem clock oscillator is to be selected. it also specifies how the cpu clock operates. css is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets css to 00h. figure 5-4. format of subclock control register cpu clock operation status 0 0 cls css0 0000 css address after reset r/w fff2h 00h r/w 76543210 cls 0 1 operation based on the output of the divided main system clock operation based on the subsystem clock selection of main system or subsystem clock oscillator css0 0 1 divided output from the main system clock oscillator output from the subsystem clock oscillator symbol note note bit 5 is read only. caution bits 0, 1, 2, 3, 6, and 7 must be fixed to 0. chapter 5 clock generator 94 user ? s manual u13952ej3v0ud 5.4 system clock oscillators 5.4.1 main system clock oscillator the main system clock oscillator is oscillated by a crystal or ceramic resonator (5.0 mhz typ.) connected across the x1 and x2 pins. an external clock can also be input to the circuit. in this case, input the clock signal to the x1 pin, and input the inverted signal to the x2 pin. figure 5-5 shows the external circuit of the main system clock oscillator. figure 5-5. external circuit of main system clock oscillator (a) crystal or ceramic oscillation (b) external clock crystal or ceramic resonator v ss0 , v ss 1 x2 x1 external clock x1 x2 caution when using the main system or subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance. ? ? ? ? keep the wiring length as short as possible. ? ? ? ? do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss0 and v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? do not fetch signals from the oscillator. chapter 5 clock generator user ? s manual u13952ej3v0ud 95 5.4.2 subsystem clock oscillator the subsystem clock oscillator is oscillated by a crystal resonator (32.768 khz typ.) connected across the xt1 and xt2 pins. an external clock can also be input to the circuit. in this case, input the clock signal to the xt1 pin, and input the inverted signal to the xt2 pin. figure 5-6 shows the external circuit of the subsystem clock oscillator. figure 5-6. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock xt2 v ss0 , v ss1 xt1 32.768 khz crystal resonator external clock xt1 xt2 caution when using the main system or subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance. ? ? ? ? keep the wiring length as short as possible. ? ? ? ? do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss0 and v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? do not fetch signals from the oscillator. when using the subsystem clock oscillator, pay special attention because the subsystem clock oscillator has low amplification to minimize current consumption. chapter 5 clock generator 96 user ? s manual u13952ej3v0ud 5.4.3 examples of incorrect resonator connection figure 5-7 shows examples of incorrect resonator connection. figure 5-7. examples of incorrect resonator connection (1/2) (a) too long wiring (b) crossed signal line v ss0 , v ss1 x1 x2 v ss0 , v ss1 x1 x2 portn (n = 0, 2, 4, 5, 6, 8, 9) (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss0 , v ss1 x1 x2 high current v ss0 , v ss1 x1 ab c pmn v dd0 , v dd1 high current x2 remark when using the subsystem clock, read x1 and x2 as xt1 and xt2, respectively, and connect resistors to the xt2 side in series. chapter 5 clock generator user ? s manual u13952ej3v0ud 97 figure 5-7. examples of incorrect resonator connection (2/2) (e) signal is fetched (f) signal lines of main system clock and subsystem clock are parallel and close together v ss0 , v ss1 x1 x2 v ss0 , v ss1 x2 xt2 is wired parallel to x1. x1 xt2 xt1 remark when using the subsystem clock, read x1 and x2 as xt1 and xt2, respectively, and connect resistors to the xt2 side in series. caution if the x1 wire is parallel with the xt2 wire, crosstalk noise may occur between x1 and xt2, resulting in a malfunction. to avoid this, do not place the x1 and xt2 wires in parallel. 5.4.4 divider the divider divides the output of the main system clock oscillator (f x ) to generate various clocks. 5.4.5 when no subsystem clock is used if a subsystem clock is not necessary, for example, for low-power consumption operation or clock operation, handle the xt1 and xt2 pins as follows: xt1: connect directly to v ss0 or v ss1 xt2: leave open in this case, however, a small current leaks via the on-chip feedback resistor in the subsystem clock oscillator when the main system clock is stopped. to avoid this, set bit 1 (frc) of the suboscillation mode register (sckm) so that the on-chip feedback resistor will not be used. also in this case, handle the xt1 and xt2 pins as stated above. chapter 5 clock generator 98 user ? s manual u13952ej3v0ud 5.5 operation of clock generator the clock generator generates the following clocks and controls the operation modes of the cpu, such as the standby mode. ? main system clock f x ? subsystem clock f xt ? cpu clock f cpu ? clock to peripheral hardware the operation of the clock generator is determined by the processor clock control register (pcc), suboscillation mode register (sckm), and subclock control register (css), as follows. (a) the slow mode (1.6 s at 5.0 mhz operation) of the main system clock is selected when the reset signal is generated (pcc = 02h). while a low level is being input to the reset pin, oscillation of the main system clock is stopped. (b) three types of minimum instruction execution time (0.4 s and 1.6 s main system clock (at 5.0 mhz operation), 122 s subsystem clock (at 32.768 khz operation)) can be selected by the pcc, sckm, and css settings. (c) two standby modes, stop and halt, can be used with the main system clock selected. in a system where no subsystem clock is used, setting bit 1 (frc) of sckm so that the on-chip feedback resistor cannot be used reduces current consumption in the stop mode. in a system where a subsystem clock is used, setting bit 0 of sckm to 1 can cause the subsystem clock to stop oscillation. (d) bit 4 (css0) of css can be used to select the subsystem clock so that low current consumption operation is used (at 122 s, 32.768 khz operation). (e) with the subsystem clock selected, it is possible to cause the main system clock to stop oscillating by setting bit 7 (mcc) of pcc. the halt mode can be used, but the stop mode cannot. (f) the clock pulse for the peripheral hardware is generated by dividing the frequency of the main system clock. the subsystem clock pulse is supplied to 8-bit timer 02, the watch timer, and the lcd controller/driver only. as a result, 8-bit timer 02 (when watch timer output is selected for the count clock when the subsystem clock is running) and the watch function can continue running even in the standby mode. the other hardware stops when the main system clock stops, because it runs based on the main system clock (except for external input clock pulses). chapter 5 clock generator user ? s manual u13952ej3v0ud 99 5.6 changing setting of system clock and cpu clock 5.6.1 time required for switching between system clock and cpu clock the cpu clock can be selected by using bit 1 (pcc1) of the processor clock control register (pcc) and bit 4 (css0) of the subclock control register (css). actually, the specified clock is not selected immediately after the setting of pcc has been changed; the old clock is used for the duration of several instructions after that (see table 5-2 ). table 5-2. maximum time required for switching cpu clock set value before switching set value after switching css0 pcc1 css0 pcc1 css0 pcc1 css0 pcc1 00011x 0 0 4 clocks 2f x /f xt clocks (306 clo cks) 1 2 clocks f x /2f xt clocks (76 clocks) 1 x 2 clocks 2 clocks remarks 1. two clocks is the minimum instruction execution time of the cpu clock before switching. 2. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. 3. x: don ? t care chapter 5 clock generator 100 user ? s manual u13952ej3v0ud 5.6.2 switching between system clock and cpu clock the following figure illustrates how the cpu clock and system clock are switched. figure 5-8. switching between system clock and cpu clock system clock cpu clock interrupt request signal reset v dd f x f x f xt f x low-speed operation high-speed operation subsystem clock operation high-speed operation wait (6.55 ms: at 5.0 mhz operation) internal reset operation <1> the cpu is reset when the reset pin is made low on power application. reset is released when the reset pin is later made high, and the main system clock starts oscillating. at this time, the oscillation stabilization time (2 15 /f x ) is automatically secured. after that, the cpu starts instruction execution at the low speed of the main system clock (1.6 s at 5.0 mhz operation). <2> after the time required for the v dd voltage to rise to the level at which the cpu can operate at the high speed has elapsed, bit 1 (pcc1) of the processor clock control register (pcc) and bit 4 (css0) of the subclock control register (css) are rewritten so that the high-speed operation can be selected. <3> a drop of the v dd voltage is detected by an interrupt request signal. the clock is switched to the subsystem clock (at this moment, the subsystem clock must be in the stable oscillation status). <4> recovery of the v dd voltage is detected by an interrupt request signal. bit 7 (mcc) of pcc is set to 0, and the main system clock starts oscillating. after the time required for the oscillation to stabilize has elapsed, pcc1 and css0 are rewritten so that high-speed operation can be selected again. caution when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. user?s manual u13952ej3v0ud 101 chapter 6 16-bit timer 50 16-bit timer 50 references the free-running counter and provides functions such as timer interrupt and timer output. in addition, the count value can be captured by a trigger pin. 6.1 function of 16-bit timer 50 16-bit timer 50 has the following functions. ? timer interrupt ? timer output ? count value capture (1) timer interrupt an interrupt is generated when the count value and compare value match. (2) timer output timer output control is possible when the count value and compare value match. (3) count value capture the count value of 16-bit timer counter 50 (tm50) is latched to the capture register in synchronization with the capture trigger and retained. chapter 6 16-bit timer 50 102 user?s manual u13952ej3v0ud 6.2 configuration of 16-bit timer 50 16-bit timer 50 consists of the following hardware. table 6-1. configuration of 16-bit timer 50 item configuration timer counter 16 bits 1 (tm50) registers compare register: 16 bits 1 (cr50) capture register: 16 bits 1 (tcp50) timer outputs 1 (to5) control registers 16-bit timer mode control register 50 (tmc50) port mode register 2 (pm2) figure 6-1. block diagram of 16-bit timer 50 cpt5/p27/ intp3 internal bus internal bus 16-bit timer mode control register 50 (tmc50) 16-bit timer mode control register 50 tof50 cpt501 cpt500 toc50 tcl501 tcl500 toe50 f x f x /2 5 edge detector 16-bit capture register 50 (tcp50) 16-bit counter read buffer 16-bit timer counter 50 (tm50) 16-bit compare register 50 (cr50) match selector ovf f/f tod50 to5/p26/ intp2 inttm50 p26 output latch pm26 chapter 6 16-bit timer 50 user ? s manual u13952ej3v0ud 103 (1) 16-bit compare register 50 (cr50) this register compares the value set to cr50 with the count value of 16-bit timer counter 50 (tm50), and when they match, generates an interrupt request (inttm50). cr50 is set using a 16-bit memory manipulation instruction. values from 0000h to ffffh can be set. reset input sets cr50 to ffffh. cautions 1. although this register is manipulated by a 16-bit memory manipulation instruction, an 8-bit memory manipulation instruction can also be used. when manipulated by an 8-bit memory manipulation instruction, the accessing method should be direct addressing. 2. when rewriting cr50 during a count operation, preset cr50 to interrupt disabled using interrupt mask flag register 1 (mk1). also, set the timer output data to inversion disabled using 16-bit timer mode control register 50 (tmc50). if cr50 is rewritten while interrupts are enabled, an interrupt request may be generated at the time of the rewrite. (2) 16-bit timer counter 50 (tm50) this is a 16-bit register that counts count pulses. tm50 is read using a 16-bit memory manipulation instruction. tm50 is in free-running mode during count clock input. reset input sets tm50 to 0000h, after which it enters free-running mode again. cautions 1. the count value after releasing stop becomes undefined because the count operation is executed during the oscillation stabilization time. 2. although this register is manipulated by a 16-bit memory manipulation instruction, an 8-bit memory manipulation instruction can also be used. when manipulated by an 8-bit memory manipulation instruction, the accessing method should be direct addressing. 3. when manipulated by an 8-bit memory manipulation instruction, readout should be performed in order from lower byte to higher byte and must be in pairs. (3) 16-bit capture register 50 (tcp50) this is a 16-bit register that captures the contents of 16-bit timer counter 50 (tm50). tcp50 is set using a 16-bit memory manipulation instruction. reset input makes tcp50 undefined. caution although this register is manipulated by a 16-bit memory manipulation instruction, an 8-bit memory manipulation instruction can also be used. when manipulated by an 8-bit memory manipulation instruction, the accessing method should be direct addressing. (4) 16-bit counter read buffer this buffer latches the counter value of 16-bit timer counter 50 (tm50) and retains the count value. chapter 6 16-bit timer 50 104 user ? s manual u13952ej3v0ud 6.3 registers controlling 16-bit timer 50 the following two registers are used to control 16-bit timer 50. ? 16-bit timer mode control register 50 (tmc50) ? port mode register 2 (pm2) (1) 16-bit timer mode control register 50 (tmc50) 16-bit timer mode control register 50 (tmc50) controls the setting of the count clock, capture edge, etc. tmc50 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc50 to 00h. chapter 6 16-bit timer 50 user ? s manual u13952ej3v0ud 105 figure 6-2. format of 16-bit timer mode control register 50 toc50 0 1 tod50 tof50 cpt501 cpt500 toc50 tcl501 tcl500 toe50 tmc50 r/w ff48h 00h r/w <6>54321 cpt501 0 0 1 1 cpt500 0 1 0 1 capture operation disabled rising edge of cpt5 falling edge of cpt5 both edges of cpt5 tof50 0 1 7 <0> set by overflow of 16-bit timer symbol address after reset timer output data inverse control inverse disabled inverse enabled capture edge selection toe50 0 1 tcl501 0 0 other than above tcl500 0 1 f x (5.0 mhz) f x /2 5 (156.3 khz) setting prohibited 16-bit timer 50 output control output disabled (port mode) output enabled tod50 0 1 timer output data timer output is ? 0 ? timer output is ? 1 ? 16-bit timer 50 count clock selection overflow flag set clear by reset and software note 1 note 2 note 3 notes 1. bit 7 is read-only. 2. if the count clock is set to f x (tcl501 = 0, tcl500 = 0), the capture function cannot be used. when reading, set the cpu clock to the main system clock high-speed mode (pcc1 = 0, css0 = 0) (see figure 5-2 ). 3. when reading, specify the main system clock as the cpu clock (pcc1 = 0, css0 = 0 or pcc1 = 1, css0 = 0) (see figure 5-2 ). remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. chapter 6 16-bit timer 50 106 user ? s manual u13952ej3v0ud (2) port mode register 2 (pm2) this register sets input/output of port 2 in 1-bit units. to use the p26/intp2/to5 pin for timer output, set pm26 and the output latch of p26 to 0. pm2 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 to ffh. figure 6-3. format of port mode register 2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2 r/w ff22h ffh r/w 654321 pm26 0 1 70 input mode (output buffer off) symbol address after reset p26 pin i/o mode selection output mode (output buffer on) chapter 6 16-bit timer 50 user ? s manual u13952ej3v0ud 107 6.4 operation of 16-bit timer 50 6.4.1 operation as timer interrupt in the timer interrupt function, interrupts are repeatedly generated at the count value set to 16-bit compare register 50 (cr50) in advance at the interval set in tcl501 and tcl500. to operate the 16-bit timer as a timer interrupt, the following settings are required. ? set the count value to cr50 ? set 16-bit timer mode control register 50 (tmc50) as shown in figure 6-4. figure 6-4. settings of 16-bit timer mode control register 50 for timer interrupt operation ? 0/1 0/1 0/1 0/1 0 0/1 0/1 tod50 tof50 cpt501 cpt500 toc50 tcl501 tcl500 toe50 tmc50 setting of count clock (see table 6-2 ) caution if both the cpt501 flag and cpt500 flag are set to 0, the capture edge becomes operation prohibited. when the count value of 16-bit timer counter 50 (tm50) matches the value set to cr50, counting of tm50 continues and an interrupt request signal (inttm50) is generated. table 6-2 shows the interval time, and figure 6-5 shows the timing of the timer interrupt operation. caution be sure to process as follows when rewriting cr50 during a count operation. <1> set interrupts to disabled (tmmk50 (bit 4 of interrupt mask flag register 1 (mk1)) = 1) <2> set the inversion control of timer output data to disabled (toc50 = 0) if cr50 is rewritten while interrupts are enabled, an interrupt request may be generated at the time of rewrite. table 6-2. interval time of 16-bit timer 50 tcl501 tcl500 count clock interval time 001/f x (0.2 s) 2 16 /f x (13.1 ms) 012 5 /f x (6.4 s) 2 21 /f x (419.4 ms) other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. chapter 6 16-bit timer 50 108 user ? s manual u13952ej3v0ud figure 6-5. timing of timer interrupt operation count clock tm50 count value cr50 inttm50 to5 tof50 0000h 0001h n ffffh 0000h 0001h n ffffh nn n nn interrupt acknowledged interrupt acknowledged overflow flag set t remark n = 0000h to ffffh chapter 6 16-bit timer 50 user ? s manual u13952ej3v0ud 109 6.4.2 operation as timer output timer outputs are repeatedly generated at the count value set to 16-bit compare register 50 (cr50) in advance at the interval set in tcl501 and tcl500. to operate 16-bit timer as a timer output, the following settings are required. ? set p26 to output mode (pm26 = 0) ? set the output latch of p26 to 0 ? set the count value to cr50 ? set 16-bit timer mode control register 50 (tmc50) as shown in figure 6-6 figure 6-6. settings of 16-bit timer mode control register 50 for timer output operation ? 0/1 0/1 0/1 1 0 0/1 1 tod50 tof50 cpt501 cpt500 toc50 tcl501 tcl500 toe50 tmc50 setting of count clock (see table 6-2 ) inverse enable of timer output data to5 output enable caution if both the cpt501 flag and cpt500 flag are set to 0, the capture edge becomes operation prohibited. when the count value of 16-bit timer counter 50 (tm50) matches the value set in cr50, the output status of the to5/intp2/p26 pin is inverted. this enables timer output. at that time, tm50 counting continues and an interrupt request signal (inttm50) is generated. figure 6-7 shows the timing of timer output (see table 6-2 for the interval time of 16-bit timer 50). figure 6-7. timer output timing note the to5 initial value becomes low level when output is enabled (toe50 = 1). remark n = 0000h to ffffh count clock tm50 count value cr50 inttm50 to5 note tof50 0000h 0001h n ffffh 0000h 0001h n ffffh nn n nn interrupt acknowledged interrupt acknowledged overflow flag set t chapter 6 16-bit timer 50 110 user ? s manual u13952ej3v0ud 6.4.3 capture operation in a capture operation, the count value of 16-bit timer counter 50 (tm50) is captured and latched to the capture register in synchronization with a capture trigger. set as shown in figure 6-8 to allow the 16-bit timer to start a capture operation. figure 6-8. settings of 16-bit timer mode control register 50 for capture operation ? 0/1 0/1 0/1 0/1 0 0/1 0/1 tod 50 tof 50 cpt501 cpt500 toc 50 tcl501 tcl500 toe 50 tmc50 count clock selection capture edge selection (see table 6-3 ) 16-bit capture register 50 (tcp50) starts a capture operation after the cpt5 capture trigger edge is defected, and latches and retains the count value of 16-bit timer counter 50 (tm50). tcp50 fetches the count value within 2 clocks and retains the count value until the next capture edge detection. table 6-3 and figure 6-9 shows the settings of the capture edge and the capture operation timing, respectively. table 6-3. settings of capture edge cpt501 cpt500 capture edge selection 0 0 capture operation prohibited 0 1 cpt5 pin rising edge 1 0 cpt5 pin falling edge 1 1 cpt5 pin both edges caution because tcp50 is rewritten when a capture trigger edge is detected during tcp50 read, disable capture trigger edge detection during tcp50 read. figure 6-9. capture operation timing (both edges of cpt5 pin are specified) count clock tm50 16-bit counter read buffer tcp50 cpt5 0000h 0000h 0001h 0001h undefined n n n m ? 1m m m capture start capture start capture edge detection capture edge detection chapter 6 16-bit timer 50 user ? s manual u13952ej3v0ud 111 6.4.4 16-bit timer counter 50 readout the count value of 16-bit timer counter 50 (tm50) is read out by a 16-bit manipulation instruction. tm50 readout is performed via a 16-bit counter read buffer. the 16-bit counter read buffer latches the tm50 count value, the buffer operation is held pending at the cpu clock falling edge after the read signal of the tm50 lower byte rises, and the count value is retained. the 16-bit counter read buffer value in the retention state can be read out as the count value. cancellation of pending is performed at the cpu clock falling edge after the read signal of the tm50 higher byte falls. reset input sets tm50 to 0000h and then to free-running mode again. figure 6-10 shows the timing of 16-bit timer counter 50 readout. cautions 1. the count value after releasing stop becomes undefined because the count operation is executed during the oscillation stabilization time. 2. aithough tm50 is manipulated by a 16-bit transfer instruction, 8-bit transfer instruction can also be used. when using an 8-bit transfer instruction, execute by direct addressing. 3. when using an 8-bit transfer instruction, execute in order from lower byte to higher byte in pairs. if the only lower byte is read, the pending state of the 16-bit counter read buffer is not canceled, and if the only higher byte is read, an undefined count value is read. figure 6-10. readout timing of 16-bit timer counter 50 cpu clock count clock tm50 16-bit counter read buffer tm50 read signal 0000h 0000h 0001h 0001h n n n + 1 read signal latch prohibited period chapter 6 16-bit timer 50 112 user ? s manual u13952ej3v0ud 6.5 cautions on using 16-bit timer 50 6.5.1 restrictions when rewriting 16-bit compare register 50 (1) disable interrupts (tmmk50 = 1) and the inversion control of timer output (toc50 = 0) before rewriting the compare register (cr50). if cr50 is rewritten with interrupts enabled, an interrupt request may be generated immediately. (2) depending on the timing of rewriting the compare register (cr50), the interval time may become twice as long as the intended time. similarly, a shorter waveform or twice-longer waveform than the intended timer output waveform may be output. to avoid this problem, rewrite the compare register using either of the following procedures. chapter 6 16-bit timer 50 user?s manual u13952ej3v0ud 113 user?s manual u13952ej3v0ud 114 chapter 7 8-bit timer/event counters 00 to 02 7.1 function of 8-bit timer/event counters 00 to 02 8-bit timer/event counters 00 to 02 have the following functions. ? interval timer (timer 00, timer 01, and timer 02) ? external event counter (timer 00 and timer 01 only) ? square-wave output (timer 02 only) the pd789407a and pd789417a subseries are provided with two 8-bit timer/event counter channels (timer 00 and timer 01) and one 8-bit timer channel (timer 02). when reading the description of timer 02, timer/event counter should be read as a timer. (1) 8-bit interval timer when the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at an arbitrary time interval set in advance. table 7-1. interval time of 8-bit timer/event counter 00 minimum interval time maximum interval time resolution 2 6 /f x (12.8 s) 2 14 /f x (3.28 ms) 2 6 /f x (12.8 s) 2 9 /f x (102.4 s) 2 17 /f x (26.2 ms) 2 9 /f x (102.4 s) remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. table 7-2. interval time of 8-bit timer/event counter 01 minimum interval time maximum interval time resolution 2 4 /f x (3.2 s) 2 12 /f x (819.2 s) 2 4 /f x (3.2 s) 2 8 /f x (51.2 s) 2 16 /f x (13.1 ms) 2 8 /f x (51.2 s) remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. table 7-3. interval time of 8-bit timer 02 minimum interval time maximum interval time resolution 2 3 /f x (1.6 s) 2 11 /f x (409.6 s) 2 3 /f x (1.6 s) 2 7 /f x (25.6 s) 2 15 /f x (6.55 ms) 2 7 /f x (25.6 s) 1/f xt (30.5 s) 2 8 /f xt (7.81 ms) 1/f xt (30.5 s) remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. chapter 7 8-bit timer/ event counters 00 to 02 user?s manual u13952ej3v0ud 115 (2) external event counter the number of pulses of an externally input signal can be measured. (3) square-wave output a square wave of any frequency can be output. table 7-4. square-wave output range of 8-bit timer 02 minimum pulse width maximum pulse width resolution 2 3 /f x (1.6 s) 2 11 /f x (409.6 s) 2 3 /f x (1.6 s) 2 7 /f x (25.6 s) 2 15 /f x (6.55 ms) 2 7 /f x (25.6 s) 1/f xt (30.5 s) 2 8 /f xt (7.81 ms) 1/f xt (30.5 s) remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. 7.2 configuration of 8-bit timer/event counters 00 to 02 8-bit timer/event counters 00 to 02 consist of the following hardware. table 7-5. configuration of 8-bit timer/event counters 00 to 02 item configuration timer counter 8 bits 3 (tm00, tm01, and tm02) register compare register: 8 bits 3 (cr00, cr01, and cr02) timer output 1 (to2) control registers 8-bit timer mode control registers 00, 01, and 02 (tmc00, tmc01, and tmc02) port mode register 2 (pm2) chapter 7 8-bit timer/ event counters 00 to 02 116 user?s manual u13952ej3v0ud figure 7-1. block diagram of 8-bit timer/event counter 00 internal bus 8-bit compare register 00 (cr00) match inttm00 f x /2 6 f x /2 9 ti0/p24/intp0 selector clear 8-bit timer counter 00 (tm00) 2 internal bus tce00 tcl001 tcl000 8-bit timer mode control register 00 (tmc00) selector figure 7-2. block diagram of 8-bit timer/event counter 01 internal bus 8-bit compare register 01 (cr01) match inttm01 selector selector clear 8-bit timer counter 01 (tm01) 2 tce01 tcl011 tcl010 8-bit timer mode control register 01 (tmc01) internal bus f x /2 4 f x /2 8 ti1/p25/intp1 chapter 7 8-bit timer/ event counters 00 to 02 user ? s manual u13952ej3v0ud 117 figure 7-3. block diagram of 8-bit timer 02 internal bus internal bus 8-bit compare register 02 (cr02) match inttm02 f x /2 3 f x /2 7 f xt clear 8-bit timer counter 02 (tm02) to2/cmptout0/ p23 2 tce02 tcl021 tcl020 toe02 8-bit timer mode control register 02 (tmc02) f/f p23 output latch pm23 comparator note selector selector selector internal bus note see chapter 12 comparator for details of the comparator. (1) 8-bit compare register 0n (cr0n) this is an 8-bit register that compares the value set to cr0n with the 8-bit timer counter 0n (tm0n) count value, and if they match, an interrupt request (inttm0n) is generated. cr0n is set using an 8-bit memory manipulation instruction. values from 00h to ffh can be set. reset input makes cr0n undefined. caution be sure to stop the operation of the timer before rewriting cr0n. if cr0n is rewritten while the timer is operation-enabled, an interrupt request match signal may be generated at the time of the rewrite. remark n = 0 to 2 (2) 8-bit timer counter 0n (tm0n) this is an 8-bit register that counts pulses. tm0n is read using an 8-bit memory manipulation instruction. reset input sets tm0n to 00h. remark n = 0 to 2 chapter 7 8-bit timer/ event counters 00 to 02 118 user ? s manual u13952ej3v0ud 7.3 registers controlling 8-bit timer/event counters 00 to 02 the following two registers are used to control 8-bit timer/event counters 00 to 02. ? 8-bit timer mode control registers 00, 01, and 02 (tmc00, tmc01, and tmc02) ? port mode register 2 (pm2) (1) 8-bit timer mode control register 00 (tmc00) tmc00 enables/stops operation of 8-bit timer counter 00 (tm00) and sets the count clock of tm00. tmc00 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc00 to 00h. figure 7-4. format of 8-bit timer mode control register 00 tce00 0000 tcl001 tcl000 0 tmc00 r/w ff53h 00h r/w 654321 tcl001 0 0 1 1 tcl000 0 1 0 1 f x /2 6 f x /2 9 tce00 0 1 ( 78.1 khz ) (9.76 khz) <7> 0 operation enabled symbol address after reset count clock selection of 8-bit timer/event counter 00 rising edge of ti0 falling edge of ti0 operation control of 8-bit timer counter 00 operation stopped (tm00 is cleared to 00h) caution be sure to stop the operation of the timer before setting tmc00. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. chapter 7 8-bit timer/ event counters 00 to 02 user ? s manual u13952ej3v0ud 119 (2) 8-bit timer mode control register 01 (tmc01) tmc01 determines whether to enable or stop operation of 8-bit timer counter 01 (tm01) and specifies the count clock for 8-bit timer/event counter 01. tmc01 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc01 to 00h. figure 7-5. format of 8-bit timer mode control register 01 tce01 0000 tcl011 tcl010 0 tmc01 symbol address after reset r/w ff57h 00h r/w 6 <7> 543210 tcl011 0 0 1 1 count clock selection of 8-bit timer/event counter 01 tcl010 0 1 0 1 f x /2 4 f x /2 8 rising edge of ti1 falling edge of ti1 tce01 0 1 operation control of 8-bit timer counter 01 operation stopped (tm01 is cleared to 00h) operation enabled (312.5 khz) (19.5 khz) caution be sure to stop the operation of the timer before setting tmc01. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. chapter 7 8-bit timer/ event counters 00 to 02 120 user ? s manual u13952ej3v0ud (3) 8-bit timer mode control register 02 (tmc02) tmc02 determines whether to enable or stop operation of 8-bit timer counter 02 (tm02) and specifies the count clock for 8-bit timer 02. it also controls the operation of the output controller. tmc02 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc02 to 00h. figure 7-6. format of 8-bit timer mode control register 02 tce02 0000 tcl021 tcl020 toe02 tmc02 symbol address after reset r/w ff5bh 00h r/w 6 <7> <0> 54321 toe02 0 1 output control of 8-bit timer 02 output disabled (port mode) output enabled tcl021 0 0 1 1 count clock selection of 8-bit timer 02 tcl020 0 1 0 1 f x /2 3 f x /2 7 f xt (32.768 khz) setting prohibited tce02 0 1 operation control of 8-bit timer counter 02 operation stopped (tm02 is cleared to 00h) operation enabled (625 khz) (39.1 khz) caution be sure to stop the operation of the timer before setting tmc02. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. chapter 7 8-bit timer/ event counters 00 to 02 user ? s manual u13952ej3v0ud 121 (4) port mode register 2 (pm2) this register sets port 2 to input/output in 1-bit units. when using the p23/comptout0/to2 pin for timer output, set pm23 and the output latch of p23 to 0. pm2 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 to ffh. figure 7-7. format of port mode register 2 pm23 0 1 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2 7654 r/w r/w 3210 input mode (output buffer off) symbol address ff22h ffh after reset p23 pin i/o mode selection output mode (output buffer on) chapter 7 8-bit timer/ event counters 00 to 02 122 user ? s manual u13952ej3v0ud 7.4 operation of 8-bit timer/event counters 00 to 02 7.4.1 operation as interval timer the interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare registers 00, 01, and 02 (cr00, cr01, and cr02) in advance. to operate the 8-bit timer/event counter as an interval timer, make the settings in the following order. <1> set 8-bit timer counter 0n (tm0n) to operation-disabled (tce0n (bit 7 of 8-bit timer mode control register 0n (tmc0n)) = 0) <2> select the count clock of the 8-bit timer/event counter (see tables 7-6 to 7-8 ) <3> set the count value to cr0n <4> set tm0n to operation-enabled (tce0n = 1) when the count value of 8-bit timer counter 0n (tm0n) matches the value set to cr0n, the value of tm0n is cleared to 00h and tm0n continues counting. at the same time, an interrupt request signal (inttm0n) is generated. tables 7-6 through 7-8 show the interval time, and figures 7-8 and 7-9 show the timing of interval timer operation. caution when the setting of the count clock using tmc0n and the setting of the tm0n to operation- enable using an 8-bit memory manipulation instruction are performed at the same time, an error of one clock or more may occur in the first cycle after the timer is started. because of this, when the 8-bit timer/event counter operates as an interval timer, be sure to make the settings in the order described above. remark n = 0 to 2 table 7-6. interval time of 8-bit timer/event counter 00 tcl001 tcl000 minimum interval time maximum interval time resolution 002 6 /f x (12.8 s) 2 14 /f x (3.28 ms) 2 6 /f x (12.8 s) 012 9 /f x (102.4 s) 2 17 /f x (26.2 ms) 2 9 /f x (102.4 s) 1 0 ti0 input cycle 2 8 ti0 input cycle ti0 i nput edge cycle 1 1 ti0 input cycle 2 8 ti0 input cycle ti0 i nput edge cycle remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. table 7-7. interval time of 8-bit timer/event counter 01 tcl011 tcl010 minimum interval time maximum interval time resolution 002 4 /f x (3.2 s) 2 12 /f x (819.2 s) 2 4 /f x (3.2 s) 012 8 /f x (51.2 s) 2 16 /f x (13.1 ms) 2 8 /f x (51.2 s) 1 0 ti1 input cycle 2 8 ti1 input cycle ti1 i nput edge cycle 1 1 ti1 input cycle 2 8 ti1 input cycle ti1 i nput edge cycle remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. chapter 7 8-bit timer/ event counters 00 to 02 user ? s manual u13952ej3v0ud 123 table 7-8. interval time of 8-bit timer 02 tcl021 tcl020 minimum interval time maximum interval time resolution 002 3 /f x (1.6 s) 2 11 /f x (409.6 s) 2 3 /f x (1.6 s) 012 7 /f x (25.6 s) 2 15 /f x (6.55 ms) 2 7 /f x (25.6 s) 101/f xt (30.5 s) 2 8 /f xt (7.81 ms) 1/f xt (30.5 s) 1 1 setting prohibited remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. figure 7-8. interval timer operation timing of timer 00 and timer 01 clear clear interrupt acknowledged interrupt acknowledged count start interval time interval time interval time count clock tm0n count value cr0n tce0n inttm0n n 01 00 n 01 00 n 00 01 nn nn t remarks 1. interval time = (n + 1) t where n = 00h to ffh 2. n = 0, 1 chapter 7 8-bit timer/ event counters 00 to 02 124 user ? s manual u13952ej3v0ud figure 7-9. interval timer operation timing of timer 02 clear clear interrupt acknowledged interrupt acknowledged count start interval time interval time interval time count clock tm02 count value cr02 tce02 inttm02 to2 n 01 00 n 01 00 n 00 01 nn nn t remark interval time = (n + 1) t where n = 00h to ffh chapter 7 8-bit timer/ event counters 00 to 02 user ? s manual u13952ej3v0ud 125 7.4.2 operation as external event counter (timer 00 and timer 01 only) the external event counter counts the number of external clock pulses input to the ti0/p24/intp0 and ti1/p25/intp1 pins by using 8-bit timer counters 00 and 01 (tm00 and tm01). to operate 8-bit timer/event counters 00 and 01 as an external event counter, make the settings in the following order. <1> set p24 and p25 to input mode (pm24 = 1, pm25 = 1) <2> set 8-bit timer counter 0n (tm0n) to operation-disabled (tce0n (bit 7 of 8-bit timer mode control register 0n (tmc0n)) = 0) <3> specify the rising edge/falling edge of tin (see tables 7-6 and 7-7 ) <4> set the count value to cr0n <5> set tm0n to operation-enabled (tce0n = 1) each time the valid edge specified by bit 1 (tcl0n0) of tmc0n is input, the value of 8-bit timer counter 0n (tm0n) is incremented. when the count value of tm0n matches the value set to cr0n, the value of tm0n is cleared to 00h and tm0n continues counting. at the same time, an interrupt request signal (inttm0n) is generated. figure 7-10 shows the timing of external event counter operation (with rising edge specified). caution when the setting of the count clock using tmc0n and the setting of the tm0n to operation- enable using an 8-bit memory manipulation instruction are performed at the same time, an error of one clock or more may occur in the first cycle after the timer is started. because of this, when the 8-bit timer/event counter operates as an external event counter, be sure to make the settings in the order described above. remark n = 0, 1 figure 7-10. external event counter operation timing (with rising edge specified) tin pin input tm0n count value cr0n tce0n inttm0n 00 01 02 03 04 05 n ? 1 n 00010203 n remarks 1. n = 00h to ffh 2. n = 0, 1 chapter 7 8-bit timer/ event counters 00 to 02 126 user ? s manual u13952ej3v0ud 7.4.3 operation as square-wave output (timer 02 only) the 8-bit timer can generate a square-wave output of any frequency at intervals specified by the count value preset to 8-bit compare register 02 (cr02). to operate 8-bit timer 02 as a square-wave output, make the settings in the following order. <1> set p23 to output mode (pm23 = 0), and set the output latch of p23 to 0 <2> disable 8-bit timer counter 02 (tm02) operation (tce02 (bit 0 of 8-bit timer mode control register 02 (tmc02)) = 1) <3> set the count clock of 8-bit timer 02 (see table 7-9 ), and enable to2 to output (toe02 (bit 0 of tmc02) = 1) <4> set the count value to cr02 <5> enable tm02 operation (tce02 = 1) when the count value of 8-bit timer counter 02 (tm02) matches the value set in cr02, the to2/p23/cmptout0 pin output is inverted. through application of this mechanism, square waves of any frequency can be output. as soon as a match occurs, the tm02 value is cleared to 00h, then counting continues count and an interrupt request signal (inttm02) is generated. setting bit 7 of tmc02 (tce02) to 0 clears the square-wave output to 0. table 7-9 lists the square-wave output range, and figure 7-11 shows the timing of square-wave output. caution when the setting of the count clock using tmc02 and the setting of the tm02 to operation- enable using an 8-bit memory manipulation instruction are performed at the same time, an error of one clock or more may occur in the first cycle after the timer is started. because of this, when the 8-bit timer operates as a square-wave output, be sure to make the settings in the order described above. table 7-9. square-wave output range of 8-bit timer 02 tcl021 tcl020 minimum pulse width maximum pulse width resolution 002 3 /f x (1.6 s) 2 11 /f x (409.6 s) 2 3 /f x (1.6 s) 012 7 /f x (25.6 s) 2 15 /f x (6.55 ms) 2 7 /f x (25.6 s) 101/f xt (30.5 s) 2 8 /f xt (7.81 ms) 1/f xt (30.5 s) 1 1 setting prohibited remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. chapter 7 8-bit timer/ event counters 00 to 02 user ? s manual u13952ej3v0ud 127 figure 7-11. square-wave output timing clear clear interrupt acknowledged interrupt acknowledged count start count clock tm02 count value cr02 tce02 inttm02 to2 note n 01 00 n 01 00 n 00 01 nn nn note the initial value of to2 when output is enabled (toe02 = 1) becomes low level. chapter 7 8-bit timer/ event counters 00 to 02 128 user ? s manual u13952ej3v0ud 7.5 cautions on using 8-bit timer/event counters 00 to 02 (1) error on starting timer an error of up to 1 clock occurs after the timer has been started until a match signal is generated. this is because 8-bit timer counters 00, 01, and 02 (tm00, tm01, and tm02) are started asynchronous to the count pulse. figure 7-12. start timing of 8-bit timer counters 00, 01, and 02 count pulse tm00, tm01, tm02 count value timer starts 00h 01h 02h 03h 04h (2) setting of 8-bit compare register 8-bit compare registers 00, 01, and 02 (cr00, cr01, and cr02) can be set to 00h. therefore, one pulse can be counted when an 8-bit timer/event counter operates as an event counter. figure 7-13. external event counter operation timing ti0, ti1 input cr00, cr01 00h tm00, tm01 count value 00h 00h 00h 00h interrupt request flag user?s manual u13952ej3v0ud 129 chapter 8 watch timer 8.1 functions of watch timer the watch timer has the following functions. watch timer interval timer the watch and interval timers can be used at the same time. figure 8-1 is a block diagram of the watch timer. figure 8-1. block diagram of watch timer f x /2 7 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler selector clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm1 wtm0 watch timer mode control register (wtm) internal bus selector chapter 8 watch timer 130 user ? s manual u13952ej3v0ud (1) watch timer the 4.19 mhz main system clock or 32.768 khz subsystem clock is used to issue an interrupt request (intwt) at 0.5-second intervals. caution when the main system clock is operating at 5.0 mhz, it cannot be used to generate a 0.5-second interval. in this case, the subsystem clock, which operates at 32.768 khz, should be used instead. (2) interval timer the interval timer is used to generate an interrupt request (intwt) at specified intervals. table 8-1. interval time of interval timer interval operation at f x = 5.0 mhz operation at f x = 4.19 mhz operation at f xt = 32.768 khz 2 4 1/f w 409.6 s 489 s 488 s 2 5 1/f w 819.2 s 978 s 977 s 2 6 1/f w 1.64 ms 1.96 ms 1.95 ms 2 7 1/f w 3.28 ms 3.91 ms 3.91 ms 2 8 1/f w 6.55 ms 7.82 ms 7.81 ms 2 9 1/f w 13.1 ms 15.6 ms 15.6 ms remark f w : watch timer clock frequency (f x /2 7 or f xt ) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency 8.2 configuration of watch timer the watch timer consists of the following hardware. table 8-2. configuration of watch timer item configuration counter 5 bits 1 prescaler 9 bits 1 control register watch timer mode control register (wtm) chapter 8 watch timer user ? s manual u13952ej3v0ud 131 8.3 register controlling watch timer the watch timer mode control register (wtm) is used to control the watch timer. watch timer mode control register (wtm) wtm selects a count clock for the watch timer and specifies whether to enable operation of the timer. it also specifies the prescaler interval and how the 5-bit counter is controlled. wtm is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets wtm to 00h. figure 8-2. format of watch timer mode control register watch timer count clock selection wtm7 wtm6 wtm5 wtm4 0 0 wtm1 wtm0 wtm symbol address after reset r/w ff4ah 00h r/w 76543210 wtm7 0 1 prescaler interval selection wtm6 0 0 0 0 1 1 2 4 /f w 2 5 /f w 2 6 /f w 2 7 /f w 2 8 /f w 2 9 /f w wtm5 0 0 1 1 0 0 (488 s) (977 s) (1.95 ms) (3.91 ms) (7.81 ms) (15.6 ms) wtm4 0 1 0 1 0 1 control of 5-bit counter operation wtm1 0 1 cleared after stop started watch timer operation wtm0 0 1 operation stopped (both prescaler and timer cleared) operation enabled other than above f x /2 7 f xt (32.768 khz) (39.1 khz) setting prohibited remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. the parenthesized values apply to operation at f w = 32.768 khz. chapter 8 watch timer 132 user ? s manual u13952ej3v0ud 8.4 operation of watch timer 8.4.1 operation as watch timer the main system clock (4.19 mhz) or subsystem clock (32.768 khz) is used as a watch timer that generates interrupts at 0.5-second intervals. by setting bits 0 and 1 (wtm0 and wtm1) of the watch timer mode control register (wtm) to 1, the watch timer starts counting. by setting them to 0, the 5-bit counter is cleared and the watch timer stops counting. when the interval timer also operates at the same time by setting wtm1 to 0, only the watch timer can be started from 0 seconds. however, an error of up to 2 9 1/f w seconds may occur for the first overflow of the watch timer (intwt) after a 0-second start, because the 9-bit prescaler is not cleared in this case. 8.4.2 operation as interval timer the interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count value. the interval time can be selected by bits 4 to 6 (wtm4 to wtm6) of the watch timer mode control register (wtm). table 8-3. interval time of interval timer wtm6 wtm5 wtm4 interval operation at f x = 5.0 mhz operation at f x = 4.19 mhz operation at f xt = 32.768 khz 0002 4 1/f w 409.6 s 489 s 488 s 0012 5 1/f w 819.2 s 978 s 977 s 0102 6 1/f w 1.64 ms 1.96 ms 1.95 ms 0112 7 1/f w 3.28 ms 3.91 ms 3.91 ms 1002 8 1/f w 6.55 ms 7.82 ms 7.81 ms 1012 9 1/f w 13.1 ms 15.6 ms 15.6 ms other than above setting prohibited remark f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency chapter 8 watch timer user ? s manual u13952ej3v0ud 133 figure 8-3. watch timer/interval timer operation timing 0h start overflow overflow 5-bit counter count clock f w /2 9 watch timer interrupt intwt interval timer interrupt intwti watch timer interrupt time (0.5 s) watch timer interrupt time (0.5 s) interval timer (t) t remark f w : watch timer clock frequency the parenthesized values apply to operation at f w = 32.768 khz. 134 user?s manual u13952ej3v0ud chapter 9 watchdog timer 9.1 functions of watchdog timer the watchdog timer has the following functions. ? watchdog timer ? interval timer caution select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (wdtm). (1) watchdog timer the watchdog timer is used to detect an inadvertent program loop. when the program loop is detected, a non-maskable interrupt or the reset signal can be generated. table 9-1. program loop detection time of watchdog timer program loop detection time operation at f x = 5.0 mhz 2 11 1/f x 410 s 2 13 1/f x 1.64 ms 2 15 1/f x 6.55 ms 2 17 1/f x 26.2 ms f x : main system clock oscillation frequency (2) interval timer the interval timer generates an interrupt at any intervals set in advance. table 9-2. interval time interval time operation at f x = 5.0 mhz 2 11 1/f x 410 s 2 13 1/f x 1.64 ms 2 15 1/f x 6.55 ms 2 17 1/f x 26.2 ms f x : main system clock oscillation frequency chapter 9 watchdog timer user?s manual u13952ej3v0ud 135 9.2 configuration of watchdog timer the watchdog timer consists of the following hardware. table 9-3. configuration of watchdog timer item configuration control registers timer clock selection register 2 (tcl2) watchdog timer mode register (wdtm) figure 9-1. block diagram of watchdog timer internal bus internal bus prescaler selector controller f x 2 6 f x 2 8 f x 2 10 3 7-bit counter clear tmif4 tmmk4 tcl22 tcl21 tcl20 timer clock selection register 2 (tcl2) watchdog timer mode register (wdtm) wdtm4 run wdtm3 intwdt maskable interrupt request reset intwdt non-maskable interrupt request f x 2 4 chapter 9 watchdog timer 136 user ? s manual u13952ej3v0ud 9.3 registers controlling watchdog timer the following two registers are used to control the watchdog timer. ? timer clock selection register 2 (tcl2) ? watchdog timer mode register (wdtm) (1) timer clock selection register 2 (tcl2) this register sets the watchdog timer count clock. tcl2 is set using an 8-bit memory manipulation instruction. reset input sets tcl2 to 00h. figure 9-2. format of timer clock selection register 2 tcl22 0 0 1 1 00000 tcl22 tcl21 tcl20 tcl2 r/w r/w 76543210 tcl21 0 1 0 1 f x /2 4 f x /2 6 f x /2 8 f x /2 10 2 11 /f x 2 13 /f x 2 15 /f x 2 17 /f x tcl20 0 0 0 0 setting prohibited symbol address ff42h 00h after reset other than above watchdog timer count clock selection interval time (410 s) (1.64 ms) (6.55 ms) (26.2 ms) (312.5 khz) (78.1 khz) (19.5 khz) (4.88 khz) remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. chapter 9 watchdog timer user ? s manual u13952ej3v0ud 137 (2) watchdog timer mode register (wdtm) this register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. wdtm is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets wdtm to 00h. figure 9-3. format of watchdog timer mode register run 0 1 selection of operation of watchdog timer note 1 run 0 0 wdtm4 wdtm3 000 wdtm symbol address after reset r/w fff9h 00h r/w <7>6543210 stop counting clear counter and start counting wdtm4 selection of operation mode of watchdog timer note 2 wdtm3 0 1 1 0 1 1 operation stopped interval timer mode (overflow and maskable interrupt occur) note 3 watchdog timer mode 1 (overflow and non-maskable interrupt occur) watchdog timer mode 2 (overflow occurs and reset operation started) 0 0 notes 1. once run has been set to (1), it cannot be cleared to (0) by software. therefore, when counting is started, it cannot be stopped by any means other than reset input. 2. once wdtm3 and wdtm4 have been set to (1), they cannot be cleared to (0) by software. 3. the watchdog timer starts operation as an interval timer when run is set to 1. cautions 1. when the watchdog timer is cleared by setting run to 1, the actual overflow time is up to 0.8% shorter than the time set by timer clock selection register 2 (tcl2). 2. in watchdog timer mode 1 or 2, set wdtm4 to 1 after confirming that tmif4 (bit 0 of interrupt request flag register 0 (if0)) is set to 0. while tmif4 is 1, a non-maskable interrupt is generated upon write completion if watchdog timer mode 1 or 2 is selected. chapter 9 watchdog timer 138 user ? s manual u13952ej3v0ud 9.4 operation of watchdog timer 9.4.1 operation as watchdog timer the watchdog timer detects an inadvertent program loop when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1. the count clock (program loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (tcl20 to tcl22) of timer clock selection register 2 (tcl2). by setting bit 7 (run) of wdtm to 1, the watchdog timer is started. set run to 1 within the set program loop detection time interval after the watchdog timer has been started. by setting run to 1, the watchdog timer can be cleared and start counting. if run is not set to 1, and the program loop detection time is exceeded, the system is reset or a non-maskable interrupt is generated by the value of bit 3 (wdtm3) of wdtm. the watchdog timer continues operation in the halt mode, but stops in the stop mode. therefore, set run to 1 before entering the stop mode to clear the watchdog timer, and then execute the stop instruction. cautions 1. the actual program loop detection time may be up to 0.8% shorter than the set time. 2. when the subsystem clock is selected as the cpu clock, the watchdog timer stops counting. table 9-4. program loop detection time of watchdog timer tcl22 tcl21 tcl20 program loop detection time operation at f x = 5.0 mhz 0002 11 1/f x 410 s 0102 13 1/f x 1.64 ms 1002 15 1/f x 6.55 ms 1102 17 1/f x 26.2 ms f x : main system clock oscillation frequency chapter 9 watchdog timer user ? s manual u13952ej3v0ud 139 9.4.2 operation as interval timer when bit 4 (wdtm4) and bit 3 (wdtm3) of the watchdog timer mode register (wdtm) are set to 0 and 1, respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time intervals specified by a preset count value. select the count clock (or interval time) by setting bits 0 to 2 (tcl20 to tcl22) of timer clock selection register 2 (tcl2). the watchdog timer starts operation as an interval timer when the run bit (bit 7 of wdtm) is set to 1. in the interval timer mode, the interrupt mask flag (tmmk4) is valid, and a maskable interrupt (intwdt) can be generated. the priority of intwdt is set as the highest of all the maskable interrupts. the interval timer continues operation in the halt mode, but stops in the stop mode. therefore, set run to 1 before entering the stop mode to clear the interval timer, and then execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (when the watchdog timer mode is selected), the interval timer mode is not set, unless the reset signal is input. 2. the interval time immediately after the setting by wdtm may be up to 0.8% shorter than the set time. table 9-5. interval time of interval timer tcl22 tcl21 tcl20 interval time operation at f x = 5.0 mhz 0002 11 1/f x 410 s 0102 13 1/f x 1.64 ms 1002 15 1/f x 6.55 ms 1102 17 1/f x 26.2 ms f x : main system clock oscillation frequency user?s manual u13952ej3v0ud 140 chapter 10 8-bit a/d converter ( pd789407a subseries) 10.1 function of 8-bit a/d converter the 8-bit a/d converter converts input analog voltages to digital signals with an 8-bit resolution. it can control up to seven analog input channels (ani0 to ani6). a/d conversion can be started only by software. one of analog inputs ani0 to ani6 is selected for a/d conversion. a/d conversion is performed repeatedly, with an interrupt request (intad0) being issued each time an a/d conversion is completed. 10.2 configuration of 8-bit a/d converter the 8-bit a/d converter consists of the following hardware. table 10-1. configuration of 8-bit a/d converter item configuration analog inputs 7 channels (ani0 to ani6) registers successive approximation register (sar) a/d conversion result register 0 (adcr0) control registers a/d converter mode register 0 (adm0) a/d input selection register 0 (ads0) chapter 10 8-bit a/d converter ( pd789407a subseries) user?s manual u13952ej3v0ud 141 figure 10-1. block diagram of 8-bit a/d converter ani0/p60 ani1/p61 ani2/p62 ani3/p63 ani4/p64 ani5/p65 ani6/p66 selector sample & hold circuit voltage comparator series resistor string successive approximation register (sar) controller 3 a/d conversion result register 0 (adcr0) tap selector av ss intad0 a/d converter mode register 0 (adm0) a/d input selection register 0 (ads0) internal bus av ss adcs0 fr02 fr01 fr00 ads02 ads01 ads00 av ref p-ch av dd (1) successive approximation register (sar) the sar receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (msb). upon receiving all the bits, down to the least significant bit (lsb), that is, upon the completion of a/d conversion, the sar sends its contents to a/d conversion result register 0 (adcr0). (2) a/d conversion result register 0 (adcr0) adcr0 holds the result of a/d conversion. each time a/d conversion ends, the conversion result received from the successive approximation register is loaded into adcr0, which is an 8-bit register that holds the result of a/d conversion. adcr0 is read using an 8-bit memory manipulation instruction. reset input makes adcr0 undefined. (3) sample & hold circuit the sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. the sampled analog input voltage is held during a/d conversion. (4) voltage comparator the voltage comparator compares an analog input with the voltage output by the series resistor string. chapter 10 8-bit a/d converter ( pd789407a subseries) 142 user ? s manual u13952ej3v0ud (5) series resistor string the series resistor string is configured between av ref and av ss . it generates the reference voltages against which analog inputs are compared. (6) ani0 to ani6 pins the ani0 to ani6 pins are analog input pins for the seven-channel a/d converter. they are used to receive the analog signals to be subject to a/d conversion. caution do not supply the ani0 to ani6 pins with voltages that fall outside the rated range. if a voltage greater than av ref or less than av ss (even if within the absolute maximum rating) is supplied to any of these pins, the conversion value for the corresponding channel will be undefined. furthermore, the conversion values for the other channels may also be affected. (7) av ref pin the av ref pin is a reference voltage pin for the a/d converter. signals received at the ani0 to ani6 pins are converted to digital signals based on the voltage across the av ref and av ss pins. (8) av ss pin the av ss pin is a ground potential pin for the a/d converter. this pin must be held at the same potential as the v ss0 pin, even while the a/d converter is not being used. (9) av dd pin the av dd pin is an analog power supply pin for the a/d converter. this pin must be held at the same potential as the v dd0 pin, even while the a/d converter is not being used. chapter 10 8-bit a/d converter ( pd789407a subseries) user ? s manual u13952ej3v0ud 143 10.3 registers controlling 8-bit a/d converter the following two registers are used to control the 8-bit a/d converter. a/d converter mode register 0 (adm0) a/d input selection register 0 (ads0) (1) a/d converter mode register 0 (adm0) adm0 specifies the conversion time for analog inputs. it also specifies whether to enable conversion. adm0 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets adm0 to 00h. figure 10-2. format of a/d converter mode register 0 a/d conversion control adcs0 0 fr02 fr01 fr00 0 0 0 adm0 symbol address after reset r/w ff80h 00h r/w <7>6543210 adcs0 0 1 a/d conversion time selection note 1 fr02 0 0 0 1 1 1 144/fx 120/fx 96/fx 72/fx 60/fx 48/fx fr01 0 0 1 0 0 1 (28.8 s) (24 s) (19.2 s) (14.4 s) (setting prohibited note 2 ) (setting prohibited note 2 ) fr00 0 1 0 0 1 0 other than above conversion stopped conversion enabled setting prohibited notes 1. the specifications of fr02, fr01, and fr00 must be such that the a/d conversion time is at least 14 s. 2. these bit combinations must not be used, as the a/d conversion time will fall below 14 s. cautions 1. the result of conversion performed immediately after bit 7 (adcs0) is set is undefined. 2. the result of conversion performed after adcs0 is cleared may be undefined (see 10.5 (5) timing that makes the a/d conversion result undefined for details). remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. chapter 10 8-bit a/d converter ( pd789407a subseries) 144 user ? s manual u13952ej3v0ud (2) a/d input selection register 0 (ads0) ads0 register specifies the port used to input the analog voltages to be converted to a digital signal. ads0 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets ads0 to 00h. figure 10-3. format of a/d input selection register 0 00000 ads02 ads01 ads00 ads0 symbol address after reset r/w ff84h 00h r/w 76543210 analog input channel specification ads02 0 0 0 0 1 1 1 1 ani0 ani1 ani2 ani3 ani4 ani5 ani6 setting prohibited ads01 0 0 1 1 0 0 1 1 ads00 0 1 0 1 0 1 0 1 caution bits 3 to 7 must be fixed to 0. chapter 10 8-bit a/d converter ( pd789407a subseries) user?s manual u13952ej3v0ud 145 10.4 operation of 8-bit a/d converter 10.4.1 basic operation of 8-bit a/d converter <1> select a channel for a/d conversion, using a/d input selection register 0 (ads0). <2> the voltage supplied to the selected analog input channel is sampled using the sample & hold circuit. <3> after sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input analog voltage until a/d conversion is completed. <4> bit 7 of the successive approximation register (sar) is set. the series resistor string voltage tap at the tap selector is set to half of av ref . <5> the series resistor string tap voltage is compared with the analog input voltage using the voltage comparator. if the analog input voltage is higher than half of av ref , the msb of the sar remains set. if it is lower than half of av ref , the msb is reset. <6> bit 6 of the sar is set automatically, and comparison shifts to the next stage. the next voltage tap of the series resistor string is selected according to bit 7, which reflects the previous comparison result, as follows: ? bit 7 = 1: three quarters of av ref ? bit 7 = 0: one quarter of av ref the tap voltage is compared with the analog input voltage. bit 6 is set or reset according to the result of comparison. ? analog input voltage tap voltage: bit 6 = 1 ? analog input voltage < tap voltage: bit 6 = 0 <7> comparison is repeated until bit 0 of the sar is reached. <8> when comparison is completed for all of the 8 bits, a significant digital result is left in the sar. this value is sent to and latched in a/d conversion result register 0 (adcr0). at the same time, it is possible to generate an a/d conversion end interrupt request (intad0). cautions 1. the first a/d conversion value immediately following the start of a/d conversion may be undefined. 2. when the a/d converter enters the standby mode, it stops operating. chapter 10 8-bit a/d converter ( pd789407a subseries) 146 user ? s manual u13952ej3v0ud figure 10-4. basic operation of 8-bit a/d converter conversion time sampling time sampling a/d conversion undefined 80h c0h or 40h conversion result conversion result a/d converter operation sar adcr0 intad0 a/d conversion continues until bit 7 (adcs0) of a/d converter mode register 0 (adm0) is reset (0) by software. if an attempt is made to write to adm0 or a/d input selection register 0 (ads0) during a/d conversion, the current a/d conversion is canceled. in this case, a/d conversion is restarted from the beginning, if the adcs0 bit is set (1). reset makes a/d conversion result register 0 (adcr0) undefined. 10.4.2 input voltage and conversion result the relationship between the analog input voltage at the analog input pins (ani0 to ani6) and the a/d conversion result (a/d conversion result register 0 (adcr0)) is represented by: adcr0 = int ( 256 + 0.5) or (adcr0 ? 0.5) v in < (adcr0 + 0.5) int( ): function that returns the integer part of a parenthesized value v in : analog input voltage av ref :av ref pin voltage adcr0: value in a/d conversion result register 0 (adcr0) figure 10-5 shows the relationship between the analog input voltage and the a/d conversion result. v in av ref av ref 256 av ref 256 chapter 10 8-bit a/d converter ( pd789407a subseries) user ? s manual u13952ej3v0ud 147 figure 10-5. relationship between analog input voltage and a/d conversion result 255 254 253 3 2 1 0 a/d conversion result (adcr0) 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 input voltage/av ref chapter 10 8-bit a/d converter ( pd789407a subseries) 148 user ? s manual u13952ej3v0ud 10.4.3 operation mode of 8-bit a/d converter the 8-bit a/d converter is initially in the select mode. in this mode, a/d input selection register 0 (ads0) is used to select an analog input channel from ani0 to ani6 for a/d conversion. a/d conversion can be started only by software, that is, by setting a/d converter mode register 0 (adm0). the a/d conversion result is saved to a/d conversion result register 0 (adcr0). at the same time, an interrupt request signal (intad0) is generated. ? ? ? ? software-started a/d conversion setting bit 7 (adcs0) of a/d converter mode register 0 (adm0) triggers a/d conversion for a voltage applied to the analog input pin specified in a/d input selection register 0 (ads0). upon completion of a/d conversion, the conversion result is saved to a/d conversion result register 0 (adcr0). at the same time, an interrupt request signal (intad0) is generated. once a/d conversion is activated, and completed, another session of a/d conversion is started. a/d conversion is repeated until new data is written to adm0. if data where the adcs0 bit is 1 is written to adm0 again during a/d conversion, the current session of a/d conversion is discontinued, and a new session of a/d conversion begins for the new data. if data where the adcs0 bit is 0 is written to adm0 again during a/d conversion, a/d conversion is stopped immediately. figure 10-6. software-started a/d conversion rewriting adm0 adcs0 = 1 rewriting adm0 adcs0 = 1 adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin anin anim conversion is discontinued; no conversion result is preserved. remarks 1. n = 0, 1, ..., 6 2. m = 0, 1, ..., 6 chapter 10 8-bit a/d converter ( pd789407a subseries) user ? s manual u13952ej3v0ud 149 10.5 cautions on using 8-bit a/d converter (1) current consumption in the standby mode when the a/d converter enters the standby mode, it stops operating. stopping conversion (bit 7 (adcs0) of a/d converter mode register 0 (adm0) = 0) can reduce the current consumption. figure 10-7 shows how to reduce the current consumption in the standby mode. figure 10-7. how to reduce current consumption in standby mode av ref av ss p-ch series resistor string adcs0 (2) input range for the ani0 to ani6 pins be sure to keep the input voltage at ani0 to ani6 within the rated range. if a voltage greater than av ref or less than av ss (even within the absolute maximum rating) is input to a conversion channel, the conversion output of the channel becomes undefined, and the conversion output of the other channels may also be affected. (3) conflict <1> conflict between writing to a/d conversion result register 0 (adcr0) at the end of conversion and reading from the adcr0 bit reading from the adcr0 bit takes precedence. after reading, the new conversion result is written to the adcr0 bit. <2> conflict between writing to the adcr0 bit at the end of conversion and writing to a/d converter mode register 0 (adm0) or a/d input selection register 0 (ads0) writing to adm0 or ads0 takes precedence. a request to write to the adcr0 bit is ignored. no a/d conversion end interrupt request signal (intad0) is generated. (4) conversion results immediately following start of a/d conversion the first a/d conversion value immediately following the start of a/d conversion may be undefined. be sure to poll the a/d conversion end interrupt request (intad0) and perform processing such as discarding the first conversion result. (5) timing that makes the a/d conversion result undefined if the timing of the end of a/d conversion and the timing of the stop of operation of the a/d converter conflict, the a/d conversion value may be undefined. because of this, be sure to read out the a/d conversion result while the a/d converter is in operation. furthermore, when reading out an a/d conversion result after a/d conversion has stopped, be sure to have done so by the time the next conversion result is complete. the conversion result readout timing is shown in figures 10-8 and 10-9. chapter 10 8-bit a/d converter ( pd789407a subseries) 150 user ? s manual u13952ej3v0ud figure 10-8. conversion result readout timing (when conversion result is undefined value) a/d conversion end a/d conversion end normal conversion result undefined value normal conversion result read out a/d operation stopped undefined value read out adcr0 intad0 adcs0 figure 10-9. conversion result readout timing (when conversion result is normal value) normal conversion result a/d conversion end normal conversion result read out a/d operation stopped adcr0 intad0 adcs0 (6) noise elimination to maintain a resolution of 8 bits, it is necessary to avoid noise at the av ref and ani0 to ani6 pins. the higher the output impedance of the analog input source, the larger the effect by noise. to eliminate noise, attach an external capacitor to the relevant pins as shown in figure 10-10. chapter 10 8-bit a/d converter ( pd789407a subseries) user ? s manual u13952ej3v0ud 151 figure 10-10. analog input pin processing reference voltage input c = 100 to 1000 pf if noise greater than av ref or less than av ss is likely to come to the av ref pin, clamp the voltage at the pin by attaching a diode with a small v f (0.3 v or lower). av ss av dd v dd0 v ss0 av ref (7) ani0 to ani6 the analog input pins (ani0 to ani6) are alternate-function pins. they are also used as port pins (p60 to p66). if any of ani0 to ani6 has been selected for a/d conversion, do not execute input instructions for the ports. otherwise, the conversion resolution may become lower. if a digital pulse is applied to a pin adjacent to the analog input pins during a/d conversion, coupling noise may occur which prevents an a/d conversion result from being attained as expected. avoid applying a digital pulse to pins adjacent to the analog input pins during a/d conversion. (8) input impedance of ani0 to ani6 pins this a/d converter charges the internal sampling capacitor for about 1/10 of the conversion time, and performs sampling. therefore at times other than sampling, only the leak current is output. during sampling, the current for charging the capacitor is also output, so the input impedance fluctuates and has no meaning. however, to ensure adequate sampling, it is recommended that the output impedance of the analog input source be set to below 10 k ? , or a 100 pf capacitor be connected to the ani0 to ani6 pins (see figure 10- 10 ). (9) input impedance of the av ref pin a series resistor string of several tens of k ? is connected across the av ref and av ss pins. if the output impedance of the reference voltage source is high, this high impedance is eventually connected in parallel with the series resistor string across the av ref and av ss pins, leading to a higher reference voltage error. chapter 10 8-bit a/d converter ( pd789407a subseries) 152 user ? s manual u13952ej3v0ud (10) interrupt request flag (adif0) changing the contents of a/d converter mode register 0 (adm0) does not clear the interrupt request flag (adif0). if the voltage at the analog input pins is changed during a/d conversion, therefore, the a/d conversion result and the conversion end interrupt request flag may reflect the previous analog input just before writing to adm0. in this case, the adif0 may appear to be set if it is read-accessed just after adm0 is write- accessed, even when a/d conversion has not been completed for the new analog input. in addition, adif0 must be cleared before a/d conversion is restarted. figure 10-11. a/d conversion end interrupt request generation timing rewriting to adm0 (to begin conversion for anin) a/d conversion adcr0 intad0 anin anin anim anin anin anim anim anim rewriting to adm0 (to begin conversion for anim) adif0 has been set, but conversion for anim has not been completed. remarks 1. n = 0, 1, ..., 6 2. m = 0, 1, ..., 6 (11) av dd pin the av dd pin is used to supply power to the analog circuit. it is also used to supply power to the ani0 to ani6 input circuit. if your application is designed to be switched to backup power, the av dd pin must be supplied with the same voltage level as for the v dd0 pin, as shown in figure 10-12. figure 10-12. av dd pin processing main power source backup capacitor v dd0 av dd v ss0 av ss user?s manual u13952ej3v0ud 153 chapter 11 10-bit a/d converter ( pd789417a subseries) 11.1 function of 10-bit a/d converter the 10-bit a/d converter converts input analog voltages to digital signals with a 10-bit resolution. it can control up to seven analog input channels (ani0 to ani6). a/d conversion can be started only by software. one of analog inputs ani0 to ani6 is selected for a/d conversion. a/d conversion is performed repeatedly, with an interrupt request (intad0) being issued each time an a/d conversion is completed. 11.2 configuration of 10-bit a/d converter the a/d converter consists of the following hardware. table 11-1. configuration of 10-bit a/d converter item configuration analog inputs 7 channels (ani0 to ani6) registers successive approximation register (sar) a/d conversion result register 0 (adcr0) control registers a/d converter mode register 0 (adm0) a/d input selection register 0 (ads0) chapter 11 10-bit a/d converter ( pd789417a subseries) 154 user?s manual u13952ej3v0ud figure 11-1. block diagram of 10-bit a/d converter ani0/p60 ani1/p61 ani2/p62 ani3/p63 ani4/p64 ani5/p65 ani6/p66 selector sample & hold circuit series resistor string voltage comparator successive approximation register (sar) controller 3 a/d conversion result register 0 (adcr0) tap selector av ss intad0 a/d converter mode register 0 (adm0) a/d input selection register 0 (ads0) internal bus av ss adcs0 fr02 fr01 fr00 ads02 ads01 ads00 av ref p-ch av dd (1) successive approximation register (sar) the sar receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (msb). upon receiving all the bits, down to the least significant bit (lsb), that is, upon the completion of a/d conversion, the sar sends its contents to a/d conversion result register 0 (adcr0). (2) a/d conversion result register 0 (adcr0) adcr0 is a 16-bit register that holds the result of a/d conversion. lower 6 bits are fixed to 0. each time a/d conversion ends, the conversion result in the successive approximation register is loaded into adcr0. the conversion results are stored in adcr0 starting from the most significant bit (msb). the higher 8 bits of the conversion results are stored in ff15h and the lower 2 bits of the conversion results are stored in ff14h. adcr0 is read using a 16-bit memory manipulation instruction. reset input makes adcr0 undefined. symbol adcr0 ff15h 0 0 0 0 0 0 ff14h ff14h, ff15h address after reset undefined r/w r caution when the pd78f9418a is used as the flash memory version of the pd789405a, 789406a, and 789407a, 8-bit access is possible, providing an object file has been assembled in the pd789405a, 789406a, and 789407a. chapter 11 10-bit a/d converter ( pd789417a subseries) user ? s manual u13952ej3v0ud 155 (3) sample & hold circuit the sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. the sampled analog input voltage is held during a/d conversion. (4) voltage comparator the voltage comparator compares an analog input with the voltage output by the series resistor string. (5) series resistor string the series resistor string is configured between av ref and av ss . it generates the reference voltages against which analog inputs are compared. (6) ani0 to ani6 pins the ani0 to ani6 pins are analog input pins for the seven-channel a/d converter. they are used to receive the analog signals to be subject to a/d conversion. caution do not supply the ani0 to ani6 pins with voltages that fall outside the rated range. if a voltage greater than av ref or less than av ss (even if within the absolute maximum rating) is supplied to any of these pins, the conversion value for the corresponding channel will be undefined. furthermore, the conversion values for the other channels may also be affected. (7) av ref pin the av ref pin is a reference voltage pin for the a/d converter. signals received at the ani0 to ani6 pins are converted to digital signals based on the voltage across the av ref and av ss pins. (8) av ss pin the av ss pin is a ground potential pin for the a/d converter. this pin must be held at the same potential as the v ss0 pin, even while the a/d converter is not being used. (9) av dd pin the av dd pin is an analog power supply pin for the a/d converter. this pin must be held at the same potential as the v dd0 pin, even while the a/d converter is not being used. chapter 11 10-bit a/d converter ( pd789417a subseries) 156 user ? s manual u13952ej3v0ud 11.3 registers controlling 10-bit a/d converter the following two registers are used to control the 10-bit a/d converter. a/d converter mode register 0 (adm0) a/d input selection register 0 (ads0) (1) a/d converter mode register 0 (adm0) adm0 specifies the conversion time for analog inputs. it also specifies whether to enable conversion. adm0 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets adm0 to 00h. figure 11-2. format of a/d converter mode register 0 a/d conversion control adcs0 0 fr02 fr01 fr00 0 0 0 adm0 symbol address after reset r/w ff80h 00h r/w <7>6543210 adcs0 0 1 a/d conversion time selection note 1 fr02 0 0 0 1 1 1 144/fx 120/fx 96/fx 72/fx 60/fx 48/fx fr01 0 0 1 0 0 1 (28.8 s) (24 s) (19.2 s) (14.4 s) (setting prohibited note 2 ) (setting prohibited note 2 ) fr00 0 1 0 0 1 0 other than above conversion stopped conversion enabled setting prohibited notes 1. the specifications of fr02, fr01, and fr00 must be such that the a/d conversion time is at least 14 s. 2. these bit combinations must not be used, as the a/d conversion time will fall below 14 s. cautions 1. the result of conversion performed immediately after bit 7 (adcs0) is set is undefined. 2. the result of conversion performed after adcs0 is cleared may be undefined (see 11.5 (5) timing that makes the a/d conversion result undefined for details). remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. chapter 11 10-bit a/d converter ( pd789417a subseries) user ? s manual u13952ej3v0ud 157 (2) a/d input selection register 0 (ads0) ads0 register specifies the port used to input the analog voltages to be converted to a digital signal. ads0 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets ads0 to 00h. figure 11-3. format of a/d input selection register 0 00000 ads02 ads01 ads00 ads0 symbol address after reset r/w ff84h 00h r/w 76543210 analog input channel specification ads02 0 0 0 0 1 1 1 1 ani0 ani1 ani2 ani3 ani4 ani5 ani6 setting prohibited ads01 0 0 1 1 0 0 1 1 ads00 0 1 0 1 0 1 0 1 caution bits 3 to 7 must be fixed to 0. chapter 11 10-bit a/d converter ( pd789417a subseries) 158 user?s manual u13952ej3v0ud 11.4 operation of 10-bit a/d converter 11.4.1 basic operation of 10-bit a/d converter <1> select a channel for a/d conversion, using a/d input selection register 0 (ads0). <2> the voltage supplied to the selected analog input channel is sampled using the sample & hold circuit. <3> after sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input analog voltage until a/d conversion is completed. <4> bit 9 of the successive approximation register (sar) is set. the series resistor string voltage tap at the tap selector is set to half of av ref . <5> the series resistor string tap voltage is compared with the analog input voltage using the voltage comparator. if the analog input voltage is higher than half of av ref , the msb of the sar remains set. if it is lower than half of av ref , the msb is reset. <6> bit 8 of the sar is set automatically, and comparison shifts to the next stage. the next voltage tap of the series resistor string is selected according to bit 9, which reflects the previous comparison result, as follows: ? bit 9 = 1: three quarters of av ref ? bit 9 = 0: one quarter of av ref the tap voltage is compared with the analog input voltage. bit 8 is set or reset according to the result of comparison. ? analog input voltage tap voltage: bit 8 = 1 ? analog input voltage < tap voltage: bit 8 = 0 <7> comparison is repeated until bit 0 of the sar is reached. <8> when comparison is completed for all of the 10 bits, a significant digital result is left in the sar. this value is sent to and latched in a/d conversion result register 0 (adcr0). at the same time, it is possible to generate an a/d conversion end interrupt request (intad0). cautions 1. the first a/d conversion value immediately following the start of a/d conversion may be undefined. 2. when the a/d converter enters the standby mode, it stops operating. chapter 11 10-bit a/d converter ( pd789417a subseries) user ? s manual u13952ej3v0ud 159 figure 11-4. basic operation of 10-bit a/d converter conversion time sampling time sampling a/d conversion undefined conversion result conversion result a/d converter operation sar adcr0 intad0 80h c0h or 40h a/d conversion continues until bit 7 (adcs0) of a/d converter mode register 0 (adm0) is reset (0) by software. if an attempt is made to write to adm0 or a/d input selection register 0 (ads0) during a/d conversion, the current a/d conversion is canceled. in this case, a/d conversion is restarted from the beginning, if the adcs0 bit is set (1). reset makes a/d conversion result register 0 (adcr0) undefined. chapter 11 10-bit a/d converter ( pd789417a subseries) 160 user ? s manual u13952ej3v0ud 11.4.2 input voltage and conversion result the relationship between the analog input voltage at the analog input pins (ani0 to ani6) and the a/d conversion result (a/d conversion result register 0 (adcr0)) is represented by: adcr0 = int ( 1024 + 0.5) or (adcr0 ? 0.5) v in < (adcr0 + 0.5) int( ): function that returns the integer part of a parenthesized value v in : analog input voltage av ref :av ref pin voltage adcr0: value in a/d conversion result register 0 (adcr0) figure 11-5 shows the relationship between the analog input voltage and the a/d conversion result. figure 11-5. relationship between analog input voltage and a/d conversion result 1023 1022 1021 3 2 1 0 a/d conversion result (adcr0) 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 input voltage/av ref v in av ref av ref 1024 av ref 1024 chapter 11 10-bit a/d converter ( pd789417a subseries) user ? s manual u13952ej3v0ud 161 11.4.3 operation mode of 10-bit a/d converter the 10-bit a/d converter is initially in the select mode. in this mode, a/d input selection register 0 (ads0) is used to select an analog input channel from ani0 to ani6 for a/d conversion. a/d conversion can be started only by software, that is, by setting a/d converter mode register 0 (adm0). the a/d conversion result is saved to a/d conversion result register 0 (adcr0). at the same time, an interrupt request signal (intad0) is generated. ? ? ? ? software-started a/d conversion setting bit 7 (adcs0) of a/d converter mode register 0 (adm0) triggers a/d conversion for a voltage applied to the analog input pin specified in a/d input selection register 0 (ads0). upon completion of a/d conversion, the conversion result is saved to a/d conversion result register 0 (adcr0). at the same time, an interrupt request signal (intad0) is generated. once a/d conversion is activated, and completed, another session of a/d conversion is started. a/d conversion is repeated until new data is written to adm0. if data where the adcs0 bit is 1 is written to adm0 again during a/d conversion, the current session of a/d conversion is discontinued, and a new session of a/d conversion begins for the new data. if data where the adcs0 bit is 0 is written to adm0 again during a/d conversion, a/d conversion is stopped immediately. figure 11-6. software-started a/d conversion rewriting adm0 adcs0 = 1 rewriting adm0 adcs0 = 1 adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin anin anim conversion is discontinued; no conversion result is preserved. remarks 1. n = 0, 1, ..., 6 2. m = 0, 1, ..., 6 chapter 11 10-bit a/d converter ( pd789417a subseries) 162 user ? s manual u13952ej3v0ud 11.5 cautions on using 10-bit a/d converter (1) current consumption in the standby mode when the a/d converter enters the standby mode, it stops operating. setting the bit 7 (adcs0) of a/d converter mode register 0 (adm0) = 0 can reduce the current consumption. figure 11-7 shows how to reduce the current consumption in the standby mode. figure 11-7. how to reduce current consumption in standby mode av ref av ss p-ch series resistor string adcs0 (2) input range for the ani0 to ani6 pins be sure to keep the input voltage at ani0 to ani6 within the rated range. if a voltage greater than av ref or less than av ss (even within the absolute maximum rating) is input a conversion channel, the conversion output of the channel becomes undefined, and the conversion output of the other channels may be affected. (3) conflict <1> conflict between writing to a/d conversion result register 0 (adcr0) at the end of conversion and reading from the adcr0 bit reading from the adcr0 bit takes precedence. after reading, the new conversion result is written to adcr0 bit. <2> conflict between writing to the adcr0 bit at the end of conversion and writing to a/d converter mode register 0 (adm0) or a/d input selection register 0 (ads0) writing to adm0 or ads0 takes precedence. a request to write to the adcr0 bit is ignored. no a/d conversion end interrupt request signal (intad0) is generated. (4) conversion results immediately following start of a/d conversion the first a/d conversion value immediately following the start of a/d conversion may be undefined. be sure to poll the a/d conversion end interrupt request (intad0) and perform processing such as discarding the first conversion result. (5) timing that makes the a/d conversion result undefined if the timing of the end of a/d conversion and the timing of the stop of operation of the a/d converter conflict, the a/d conversion value may be undefined. because of this, be sure to read out the a/d conversion result while the a/d converter is in operation. furthermore, when reading out an a/d conversion result after a/d conversion has stopped, be sure to have done so by the time the next conversion result is complete. the conversion result readout timing is shown in figures 11-8 and 11-9. chapter 11 10-bit a/d converter ( pd789417a subseries) user ? s manual u13952ej3v0ud 163 figure 11-8. conversion result readout timing (when conversion result is undefined value) a/d conversion end a/d conversion end normal conversion result undefined value normal conversion result read out a/d operation stopped undefined value read out adcr0 intad0 adcs0 figure 11-9. conversion result readout timing (when conversion result is normal value) normal conversion result a/d conversion end normal conversion result read out a/d operation stopped adcr0 intad0 adcs0 (6) noise elimination to maintain a resolution of 10 bits, it is necessary to avoid for noise at the av ref and ani0 to ani6 pins. the higher the output impedance of the analog input source, the larger the effect by noise. to eliminate noise, attach an external capacitor to the relevant pins as shown in figure 11-10. chapter 11 10-bit a/d converter ( pd789417a subseries) 164 user?s manual u13952ej3v0ud figure 11-10. analog input pin processing reference voltage input c = 100 to 1000 pf if noise greater than av ref or less than av ss is likely to come to the av ref pin, clamp the voltage at the pin by attaching a diode with a small v f (0.3 v or lower). av ss av dd v dd0 v ss0 av ref (7) ani0 to ani6 the analog input pins (ani0 to ani6) are alternate-function pins. they are also used as port pins (p60 to p66). if any of ani0 to ani6 has been selected for a/d conversion, do not execute input instructions for the ports. otherwise, the conversion resolution may become lower. if a digital pulse is applied to a pin adjacent to the analog input pins during a/d conversion, coupling noise may occur which prevents an a/d conversion result from being attained as expected. avoid applying a digital pulse to pins adjacent to the analog input pins during a/d conversion. (8) input impedance of ani0 to ani6 pins this a/d converter charges the internal sampling capacitor for about 1/10 of the conversion time, and performs sampling. therefore at times other than sampling, only the leak current is output. during sampling, the current for charging the capacitor is also output, so the input impedance fluctuates and has no meaning. however, to ensure adequate sampling, it is recommended that the output impedance of the analog input source be set to below 10 k ? , or a 100 pf capacitor be connected to the ani0 to ani6 pins (see figure 11- 10 ). (9) input impedance of the av ref pin a series resistor string of 10 k ? is connected across the av ref and av ss pins. if the output impedance of the reference voltage source is high, this high impedance is eventually connected in parallel with the series resistor string across the av ref and av ss pins, leading to a higher reference voltage error. chapter 11 10-bit a/d converter ( pd789417a subseries) user ? s manual u13952ej3v0ud 165 (10) interrupt request flag (adif0) changing the contents of a/d converter mode register 0 (adm0) does not clear the interrupt request flag (adif0). if the voltage at the analog input pins is changed during a/d conversion, therefore, the a/d conversion result and the conversion end interrupt request flag may reflect the previous analog input just before writing to adm0. in this case, the adif0 may appear to be set if it is read-accessed just after adm0 is write- accessed, even when a/d conversion has not been completed for the new analog input. in addition, adif0 must be cleared before a/d conversion is restarted. figure 11-11. a/d conversion end interrupt request generation timing rewriting to adm0 (to begin conversion for anin) a/d conversion adcr0 intad0 anin anin anim anin anin anim anim anim rewriting to adm0 (to begin conversion for anim) adif0 has been set, but conversion for anim has not been completed. remarks 1. n = 0, 1, ..., 6 2. m = 0, 1, ..., 6 (11) av dd pin the av dd pin is used to supply power to the analog circuit. it is also used to supply power to the ani0 to ani6 input circuit. if your application is designed to be changed to backup power, the av dd pin must be supplied with the same voltage level as for the v dd0 pin, as shown in figure 11-12. figure 11-12. av dd pin processing main power source backup capacitor v dd0 av dd v ss0 av ss user?s manual u13952ej3v0ud 166 chapter 12 comparator 12.1 functions of comparator the comparator has the following functions. (1) input voltage comparison by comparator the comparator compares an input voltage at the reference voltage input pin (cmpref0) with an input voltage at the comparator input pin (cmpin0). the comparison result can be read using memory manipulation instructions. (2) interrupt generation by comparator output the comparator output is used to generate an interrupt request signal note (intcmp0). note the rising edge, falling edge, or both rising and falling edges can be specified by setting external interrupt mode register 1 (intm1). (3) clock output when cmpref0 > cmpin0, the output of 8-bit timer counter 02 (tm02) is directed to the cmptout0 pin. (4) open-drain output selection comparator mode register 0 (cmprm0) is used to specify a port as an n-ch open-drain output. chapter 12 comparator user?s manual u13952ej3v0ud 167 12.2 configuration of comparator the comparator consists of the following hardware. (1) cmpin0 this is the comparator input pin. (2) cmptout0 this is the comparator output pin. (3) cmpref0 this is the comparator reference voltage input pin. figure 12-1 is a block diagram of the comparator. figure 12-1. block diagram of comparator internal bus p23 output latch pm23 selector timing control cmptout0/p23/ to2 _ + cmpin0 cmpref0 intcmp0 8-bit timer 02 (tm02) output edge selector internal bus comparator mode register 0 (cmprm0) es61 external interrupt mode register 1 (intm1) cmpon0 cmpout0 selcmp0 opdr0 es60 chapter 12 comparator 168 user ? s manual u13952ej3v0ud 12.3 register controlling comparator the comparator is controlled by the following register. (1) comparator mode register 0 (cmprm0) cmprm0 controls the power supply and clock output of the comparator. it also selects an open-drain output for the comparator. cmprm0 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets cmprm0 to 00h. figure 12-2. format of comparator mode register 0 cmpon0 0 1 comparator power supply on/off control 000 cmpon0 selcmp0 opdr0 cmpout0 cmprm0 symbol address after reset r/w ff4eh 00h r/w note 6 7 543210 selcmp0 0 1 clock output control opdr0 0 1 open-drain output selection cmpout0 0 comparator power supply off comparator power supply on 8-bit timer 02 (tm02) output 8-bit timer counter 02 (tm02) output if cmpref0 > cmpin0 cmos output n-ch open-drain output the comparator output is read. note bit 0 is read-only. cautions 1. bits 4 to 7 must be fixed to 0. 2. if the comparator is enabled (cmpon0 = 1), noise may be induced. if it is necessary to generate an interrupt request signal (intcmp0) from the output of the comparator, enable the comparator (cmpon0 = 1), then clear the interrupt request flag (cmpif0) to 0, before enabling interrupts. 3. similarly, if it is necessary to direct the output of the comparator to the port, enable the comparator (cmpon0 = 1) in advance. chapter 12 comparator user ? s manual u13952ej3v0ud 169 12.4 operation of comparator the output of 8-bit timer 02 (tm02) can be controlled and directed to the cmptout0/p23/to2 pin via the comparator. to run the comparator, set as follows: ? set p23 to output mode (pm23 = 0). ? set comparator mode register 0 (cmprm0) as shown in figure 12-3. ? set external interrupt mode register 1 (intm1) as shown in figure 12-4 and select the valid edge of intcmp0. figure 12-3. settings of comparator mode register 0 for comparator operation figure 12-4. settings of external interrupt mode register 1 at intcmp0 occurrence 0/1 0/1 0 0 1 1 0/1 0/1 es61 intm1 es60 es31 selects the valid edge (see table 12-1 ). es30 table 12-1 lists the selection of intcmp0 valid edges, and figure 12-5 shows the timing chart of the comparator. table 12-1. intcmp0 valid edges es61 es60 intcmp0 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 0 cmprm0 000110/1 ? cmpon0 selcmp0 opdr0 cmpout0 outputs tm02. switches on the comparator power. chapter 12 comparator 170 user ? s manual u13952ej3v0ud figure 12-5. comparator operation timing (1/2) timer (tm02) output cmpout0 cmptout0 selcmp0 timer (tm02) output enable signal <1> cmpout0 is latched on the rising edge of the tm02 output to generate a signal to enable output to the cmptout0/p23/to2 pin. if cmpout0 is high, the tm02 output waveform is output to the cmptout0/p23/to2 pin on the rising edge of the tm02 output. if cmpout0 is low, cmptout0 is not output. <2> if selcmp0 is low, the tm02 output is sent to the cmptout0/p23/to2 pin no matter which level cmpout0 is on. figure 12-5. comparator operation timing (2/2) timer (tm02) output cmpout0 cmptout0 selcmp0 timer (tm02) output enable signal <3> if the high level of cmpout0 is latched on the rising edge of the tm02 output, cmptout0 is output to the cmptout0/p23/to2 pin for at least two clock pulses even if it falls immediately. <4> switching selcmp0 from high to low during cmptout0 output may disturb the output waveform of cmptout0. user?s manual u13952ej3v0ud 171 chapter 13 serial interface 00 13.1 functions of serial interface 00 serial interface 00 has the following three modes. ? operation stopped mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode (1) operation stopped mode this mode is used to reduce power consumption when serial transfer is not carried out. (2) asynchronous serial interface (uart) mode in this mode, one byte of data following the start bit is transmitted/received, and full-duplex operation is possible. a dedicated uart baud rate generator is incorporated, allowing communication over a wide range of baud rates. in addition, the baud rate can be defined by dividing the clock input to the asck pin. (3) 3-wire serial i/o mode (msb/lsb start bit switchable) in this mode, 8-bit data transfer is carried out using three lines, one for the serial clock (sck) and two for serial data (si, so). the 3-wire serial i/o mode supports simultaneous transmit and receive operations, reducing data transfer processing time. it is possible to switch the start bit of 8-bit data to be transmitted between the msb and the lsb, thus allowing connection to devices with either start bit. the 3-wire serial i/o mode is effective for connecting display controllers and peripheral i/os such as the 75xl series, 78k series, and 17k series, which have conventional clock synchronous serial interfaces. chapter 13 serial interface 00 172 user?s manual u13952ej3v0ud 13.2 configuration of serial interface 00 serial interface 00 consists of the following hardware. table 13-1. configuration of serial interface 00 item configuration registers transmit shift register 00 (txs00) receive shift register 00 (rxs00) receive buffer register 00 (rxb00) control registers serial operation mode register 00 (csim00) asynchronous serial interface mode register 00 (asim00) asynchronous serial interface status register 00 (asis00) baud rate generator control register 00 (brgc00) chapter 13 serial interface 00 user?s manual u13952ej3v0ud 173 pe00 fe00 ove00 intsr00/intcsi00 rxd/si/p22 txd/so/p21 pm21 pm20 txe00 rxe00 ps001 ps000 cl00 sl00 intst00 csie00 dir00 csck00 tps003 tps002 tps001 tps000 4 csie00 txe00 rxe00 csck00 asck/sck/p20 f x /2 to f x /2 8 internal bus internal bus receive buffer register 00 (rxb00/sio00) direction controller receive shift register 00 (rxs00) receive controller asynchronous serial interface status register 00 (asis00) direction controller asynchronous serial interface mode register 00 (asim00) transmit controller sck output controller baud rate generator note baud rate generator control register 00 (brgc00) serial operation mode register 00 (csim00) transmit shift register 00 (txs00/sio00) figure 13-1. block diagram of serial interface 00 note for the baud rate generator configuration, see figure 13-2. chapter 13 serial interface 00 174 user ? s manual u13952ej3v0ud f x 2 f x 2 2 f x 2 3 f x 2 4 f x 2 5 f x 2 6 f x 2 7 f x 2 8 tps003 tps002 tps001 tps000 4 csie00 txe00 rxe00 asck/sck/p20 1/2 1/2 csie00 rxe00 csie00 internal bus brgc00 write txe00 csck00 rxe00 transmit clock receive clock selector clear clear 3-bit counter clear 3-bit counter clear stop prescaler baud rate generator control register 00 (brgc00) selector selector start bit detection brgc00 write figure 13-2. block diagram of baud rate generator chapter 13 serial interface 00 user ? s manual u13952ej3v0ud 175 (1) transmit shift register 00 (txs00) this register is used to specify data to be transmitted. data written to txs00 is transmitted as serial data. if the data length is specified as 7 bits, bits 0 to 6 of the data written to txs00 are transferred as the transmit data. the transmit operation is started by writing data to txs00. txs00 is written to using an 8-bit memory manipulation instruction. it cannot be read. reset input sets txs00 to ffh. caution do not write to txs00 during a transmit operation. txs00 and receive buffer register 00 (rxb00) are allocated to the same address, and when reading is performed, rxb00 values are read. (2) receive shift register 00 (rxs00) this register is used to convert serial data input to the rxd pin into parallel data. each time one byte of data is received, it is transferred to receive buffer register 00 (rxb00). rxs00 cannot be manipulated directly by program. (3) receive buffer register 00 (rxb00) this register is used to hold received data. each time one byte of data is received, a new byte of data is transferred from receive shift register 00 (rxs00). if the data length is specified as 7 bits, receive data is transferred to bits 0 to 6 of rxb00, and the msb of rxb00 always becomes 0. rxb00 can be read using an 8-bit memory manipulation instruction. it cannot be written to. reset input makes rxb00 undefined. caution rxb00 and transmit shift register 00 (txs00) are allocated to the same address, and when writing is performed, the values are written to txs00. (4) transmit controller this circuit controls transmit operations by adding a start bit, parity bit, and stop bit to data written to transmit shift register 00 (txs00), according to the data set to asynchronous serial interface mode register 00 (asim00). (5) receive controller this circuit controls receive operations according to the data set to asynchronous serial interface mode register 00 (asim00). it also performs a parity error check, etc., during receive operations, and when an error is detected, it sets a value to asynchronous serial interface status register 00 (asis00) in accordance with the nature of the error. chapter 13 serial interface 00 176 user?s manual u13952ej3v0ud 13.3 registers controlling serial interface 00 the following four registers are used to control serial interface 00. ? serial operation mode register 00 (csim00) ? asynchronous serial interface mode register 00 (asim00) ? asynchronous serial interface status register 00 (asis00) ? baud rate generator control register 00 (brgc00) (1) serial operation mode register 00 (csim00) this register is set when using serial interface 00 in the 3-wire serial i/o mode. csim00 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets csim00 to 00h. figure 13-3. format of serial operation mode register 00 csie00 0 1 operation control in 3-wire serial i/o mode csie00 0000 dir00 csck00 0 csim00 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation stopped operation enabled dir00 0 1 start bit specification msb lsb csck00 0 1 clock selection in 3-wire serial i/o mode clock input to sck pin from external dedicated baud rate generator output cautions 1. bits 0 and 3 to 6 must be fixed to 0. 2. set csim00 to 00h in the uart mode. chapter 13 serial interface 00 user ? s manual u13952ej3v0ud 177 (2) asynchronous serial interface mode register 00 (asim00) this register is set when using serial interface 00 in the asynchronous serial interface mode. asim00 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets asim00 to 00h. figure 13-4. format of asynchronous serial interface mode register 00 txe00 0 1 transmit operation control txe00 rxe00 ps001 ps000 cl00 sl00 0 0 asim00 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe00 0 1 0 1 0 0 0 1 0 1 1 1 no parity 0 parity always added at transmission parity check is not performed at reception (no parity error occurs) odd parity even parity receive operation control ps001 parity bit specification ps000 cl00 0 1 sl00 character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification cautions 1. bits 0 and 1 must be fixed to 0. 2. set asim00 to 00h in the 3-wire serial i/o mode. 3. switching operation modes must be performed after the serial transmit/receive operation is stopped. chapter 13 serial interface 00 178 user ? s manual u13952ej3v0ud table 13-2. operation mode settings of serial interface 00 (1) operation stopped mode p22/si/rxd p21/so/txd p20/sck/asck p22 p21 p20 asim00 txe00 0 rxe00 0 csie00 0 csim00 dir00 x csck00 x pm22 x note 1 p22 x note 1 pm21 x note 1 p21 x note 1 pm20 x note 1 p20 x note 1 ? ? other than above setting prohibited start bit shift clock pin function pin function pin function (2) asynchronous serial interface mode p22/si/rxd p21/so/txd p20/sck/asck lsb p22 rxd txd (cmos output) p21 txd (cmos output) asck input p20 asck input p20 asck input p20 asim00 txe00 1 0 1 rxe00 0 1 1 csie00 0 0 0 csim00 dir00 0 0 0 csck00 0 0 0 pm22 x note 1 1 1 p22 x note 1 x x pm21 0 x note 1 0 p21 1 x note 1 1 pm20 1 x note 1 1 x note 1 1 x note 1 p20 x x note 1 x x note 1 x x note 1 other than above start bit shift clock pin function pin function pin function external clock external clock external clock internal clock internal clock internal clock setting prohibited (3) 3-wire serial i/o mode msb lsb si note 2 so (cmos output) sck input sck output 0 0 1 1 0 1 0 1 0 1 1 note 2 x note 2 0 1 1 0 1 0 x 1 x 1 external clock external clock internal clock internal clock other than above setting prohibited p22/si/rxd p21/so/txd p20/sck/asck asim00 txe00 rxe00 csie00 csim00 dir00 csck00 pm22 p22 pm21 p21 pm20 p20 start bit shift clock pin function pin function pin function sck input sck output notes 1. can be used as port function. 2. if used only for transmission, can be used as p22 (cmos i/o). remark x: don ? t care chapter 13 serial interface 00 user ? s manual u13952ej3v0ud 179 (3) asynchronous serial interface status register 00 (asis00) this register indicates the type of error when a reception error occurs in the asynchronous serial interface mode. asis00 is read using a 1-bit or 8-bit memory manipulation instruction. the contents of asis00 become undefined in the 3-wire serial i/o mode. reset input sets asis00 to 00h. figure 13-5. format of asynchronous serial interface status register 00 pe00 0 1 parity error flag 00000 pe00 fe00 ove00 asis00 symbol address after reset r/w ff71h 00h r 76543210 parity error did not occur parity error occurred (when the transmit parity and receive parity did not match) framing error did not occur framing error occurred (when stop bit was not detected) note 1 overrun error did not occur overrun error occurred note 2 (when the next receive operation was completed before the data was read from receive buffer register 00) fe00 0 1 0 1 framing error flag overrun error flag ove00 notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl00) of asynchronous serial interface mode register 00 (asim00), only one stop bit is detected during reception. 2. be sure to read receive buffer register 00 (rxb00) when an overrun error occurs. if not, an overrun error will occur every time the data is received. chapter 13 serial interface 00 180 user ? s manual u13952ej3v0ud (4) baud rate generator control register 00 (brgc00) this register is used to set the serial clock of serial interface 00. brgc00 is set using an 8-bit memory manipulation instruction. reset input sets brgc00 to 00h. figure 13-6. format of baud rate generator control register 00 tps003 0 0 0 0 0 0 0 0 1 tps003 tps002 tps001 tps000 0000 brgc00 r/w ff73h 00h r/w 76543210 tps002 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) tps001 0 0 1 1 0 0 1 1 0 tps000 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 ? setting prohibited symbol address after reset 3-bit counter source clock selection clock input from external to asck pin note other than above note only used in the uart mode. cautions 1. when brgc00 is written during a communication operation, the output of the baud rate generator is disrupted and communications cannot be performed normally. be sure not to write to brgc00 during a communication operation. 2. do not select n = 1 during f x = 5.0 mhz operation because the baud rate rating is exceeded. remarks 1. f x : main system clock oscillation frequency 2. n: value determined in the settings of tps000 to tps003 (1 n 8) 3. the parenthesized values apply to operation at f x = 5.0 mhz. chapter 13 serial interface 00 user ? s manual u13952ej3v0ud 181 the baud rate transmit/receive clock to be generated is either a signal divided from the main system clock, or a signal divided from the clock input from the asck pin. (a) generation of baud rate transmit/receive clock from main system clock the transmit/receive clock is generated by dividing the main system clock. the baud rate generated from the main system clock is estimated by using the following expression. [baud rate] = [hz] f x : main system clock oscillation frequency n: value in figure 13-6 that is determined in the settings of tps000 to tps003 (2 n 8) table 13-3. example of relationship between main system clock and baud rate baud rate brgc00 set value error (%) (bps) f x = 5.0 mhz f x = 4.9152 mhz 1200 70h 1.73 0 2400 60h 4800 50h 9600 40h 19200 30h 38400 20h 76800 10h f x 2 n + 1 8 chapter 13 serial interface 00 182 user ? s manual u13952ej3v0ud (b) generation of baud rate transmit/receive clock from external clock of asck pin the transmit/receive clock is generated by dividing the clock input from the asck pin. the baud rate generated from the clock input from the asck pin is estimated by using the following expression. [baud rate] = [hz] f asck : frequency of clock input to the asck pin table 13-4. relationship between asck pin input frequency and baud rate (when brgc00 is set to 80h) baud rate (bps) asck pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1200 19.2 2400 38.4 4800 76.8 9600 153.6 19200 307.2 31250 500.0 38400 614.4 f asck 16 chapter 13 serial interface 00 user ? s manual u13952ej3v0ud 183 13.4 operation of serial interface 00 serial interface 00 has the following three modes. ? operation stopped mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode 13.4.1 operation stopped mode serial transfer is not executed in the operation stopped mode, therefore the power consumption can be reduced. the p20/sck/asck, p21/so/txd, and p22/si/rxd pins can be used as normal i/o port pins. (1) register setting operation stopped mode is set by serial operation mode register 00 (csim00) and asynchronous serial interface mode register 00 (asim00). (a) serial operation mode register 00 (csim00) csim00 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets csim00 to 00h. csie00 0 1 operation control in 3-wire serial i/o mode csie00 0000 dir00 csck00 0 csim00 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation stopped operation enabled caution bits 0 and 3 to 6 must be fixed to 0. chapter 13 serial interface 00 184 user ? s manual u13952ej3v0ud (b) asynchronous serial interface mode register 00 (asim00) asim00 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets asim00 to 00h. txe00 0 1 transmit operation control txe00 rxe00 ps001 ps000 cl00 sl00 0 0 asim00 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe00 0 1 receive operation control caution bits 0 and 1 must be fixed to 0. chapter 13 serial interface 00 user ? s manual u13952ej3v0ud 185 13.4.2 asynchronous serial interface (uart) mode in this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communications are possible. this device incorporates a uart-dedicated baud rate generator, enabling communication at the desired baud rate. in addition, the baud rate can also be defined by dividing the clock input to the asck pin. the uart-dedicated baud rate generator can also output a 31.25 kbps baud rate, which complies with the midi standard. (1) register setting uart mode is set by serial operation mode register 00 (csim00), asynchronous serial interface mode register 00 (asim00), asynchronous serial interface status register 00 (asis00), and baud rate generator control register 00 (brgc00). (a) serial operation mode register 00 (csim00) csim00 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets csim00 to 00h. set csim00 to 00h in the uart mode. csie00 0 1 operation control in 3-wire serial i/o mode csie00 0000 dir00 csck00 0 csim00 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation stopped operation enabled dir00 0 1 start bit specification msb lsb csck00 0 1 clock selection in 3-wire serial i/o mode clock input to sck pin from external dedicated baud rate generator output caution bits 0 and 3 to 6 must be fixed to 0. chapter 13 serial interface 00 186 user ? s manual u13952ej3v0ud (b) asynchronous serial interface mode register 00 (asim00) asim00 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets asim00 to 00h. txe00 0 1 transmit operation control txe00 rxe00 ps001 ps000 cl00 sl00 0 0 asim00 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe00 0 1 0 1 0 0 0 1 0 1 1 1 no parity 0 parity always added at transmission parity check is not performed at reception (no parity error occurs) odd parity even parity receive operation control ps001 parity bit specification ps000 cl00 0 1 sl00 character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification cautions 1. bits 0 and 1 must be fixed to 0. 2. switching operation modes must be performed after the serial transmit/receive operation is stopped. chapter 13 serial interface 00 user?s manual u13952ej3v0ud 187 (c) asynchronous serial interface status register 00 (asis00) asis00 is read using a 1-bit or 8-bit memory manipulation instruction. reset input sets asis00 to 00h. pe00 0 1 parity error flag 00000 pe00 fe00 ove00 asis00 symbol address after reset r/w ff71h 00h r 76543210 parity error did not occur parity error occurred (when the transmit parity and receive parity did not match) framing error did not occur framing error occurred (when stop bit was not detected) note 1 overrun error did not occur overrun error occurred note 2 (when the next receive operation was completed before the data was read from receive buffer register 00) fe00 0 1 0 1 framing error flag overrun error flag ove00 notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl00) of asynchronous serial interface mode register 00 (asim00), only one stop bit will be detected during reception. 2. be sure to read receive buffer register 00 (rxb00) when an overrun error occurs. if not, every time the data is received an overrun error occurs. chapter 13 serial interface 00 188 user ? s manual u13952ej3v0ud (d) baud rate generator control register 00 (brgc00) brgc00 is set using an 8-bit memory manipulation instruction. reset input sets brgc00 to 00h. tps003 0 0 0 0 0 0 0 0 1 tps003 tps002 tps001 tps000 0000 brgc00 r/w ff73h 00h r/w 76543210 tps002 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) tps001 0 0 1 1 0 0 1 1 0 tps000 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 setting prohibited symbol address after reset 3-bit counter source clock selection clock input from external to asck pin other than above cautions 1. when brgc00 is written during a communication operation, the output of the baud rate generator is disrupted and communications cannot be performed normally. be sure not to write to brgc00 during a communication operation. 2. do not select n = 1 during f x = 5.0 mhz operation because the baud rate rating is exceeded. remarks 1. f x : main system clock oscillation frequency 2. n: value determined in the settings of tps000 to tps003 (1 n 8) 3. the parenthesized values apply to operation at f x = 5.0 mhz. chapter 13 serial interface 00 user ? s manual u13952ej3v0ud 189 the baud rate transmit/receive clock to be generated is either a signal divided from the main system clock, or a signal divided from the clock input from the asck pin. (i) generation of baud rate transmit/receive clock from main system clock the transmit/receive clock is generated by dividing the main system clock. the baud rate generated from the main system clock is estimated by using the following expression. [baud rate] = [hz] f x : main system clock oscillation frequency n: value in the above table that is determined in the settings of tps000 to tps003 (2 n 8) table 13-5. example of relationship between main system clock and baud rate baud rate brgc00 set value error (%) (bps) f x = 5.0 mhz f x = 4.9152 mhz 1200 70h 1.73 0 2400 60h 4800 50h 9600 40h 19200 30h 38400 20h 76800 10h f x 2 n + 1 8 chapter 13 serial interface 00 190 user ? s manual u13952ej3v0ud (ii) generation of baud rate transmit/receive clock from external clock of asck pin the transmit/receive clock is generated by dividing the clock input from the asck pin. the baud rate generated from the clock input from the asck pin is estimated by using the following expression. [baud rate] = [hz] f asck : frequency of clock input to the asck pin table 13-6. relationship between asck pin input frequency and baud rate (when brgc00 is set to 80h) baud rate (bps) asck pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1200 19.2 2400 38.4 4800 76.8 9600 153.6 19200 307.2 31250 500.0 38400 614.4 f asck 16 chapter 13 serial interface 00 user ? s manual u13952ej3v0ud 191 (2) communication operation (a) data format the transmit/receive data format is as shown in figure 13-7. one data frame consists of a start bit, character bits, parity bit and stop bit(s). the specification of character bit length, parity selection, and specification of stop bit length for each data frame is carried out using asynchronous serial interface mode register 00 (asim00). figure 13-7. format of asynchronous serial interface transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit start bit one data frame ? start bit ...................... 1 bit ? character bits............. 7 bits/8 bits ? parity bits ................... even parity/odd parity/0 parity/no parity ? stop bit(s)................... 1 bit/2 bits when 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; the most significant bit (bit 7) is ignored in transmission, and the most significant bit (bit 7) is always 0 in reception. the serial transfer rate is selected using asim00 and baud rate generator control register 00 (brgc00). if a serial data receive error occurs, the receive error contents can be determined by reading the status of asynchronous serial interface status register 00 (asis00). chapter 13 serial interface 00 192 user ? s manual u13952ej3v0ud (b) parity types and operation the parity bit is used to detect a bit error in the communication data. normally, the same kind of parity bit is used on the transmitting side and the receiving side. with even parity and odd parity, a ? 1 ? bit (odd number) error can be detected. with 0 parity and no parity, an error cannot be detected. (i) even parity ? ? ? ? at transmission the transmission operation is controlled so that the number of bits with a value of 1 in the transmit data including the parity bit may be even. the parity bit value should be as follows. the number of bits with a value of 1 is an odd number in transmit data: 1 the number of bits with a value of 1 is an even number in transmit data: 0 ? ? ? ? at reception the number of bits with a value of 1 in the receive data including the parity bit is counted, and if the number is odd, a parity error occurs. (ii) odd parity ? ? ? ? at transmission conversely to even parity, the transmission operation is controlled so that the number of bits with a value of 1 in the transmit data including the parity bit may be odd. the parity bit value should be as follows. the number of bits with a value of 1 is an odd number in transmit data: 0 the number of bits with a value of 1 is an even number in transmit data: 1 ? ? ? ? at reception the number of bits with a value of 1 in the receive data including the parity bit is counted, and if the number is even, a parity error occurs. (iii) 0 parity when transmitting, the parity bit is set to 0 irrespective of the transmit data. at reception, a parity bit check is not performed. therefore, a parity error does not occur, irrespective of whether the parity bit is set to 0 or 1. (iv) no parity a parity bit is not added to the transmit data. at reception, data is received assuming that there is no parity bit. since there is no parity bit, a parity error does not occur. chapter 13 serial interface 00 user ? s manual u13952ej3v0ud 193 (c) transmission a transmit operation is started by writing transmit data to transmit shift register 00 (txs00). the start bit, parity bit and stop bit(s) are added automatically. when the transmit operation starts, the data in txs00 is shifted out, and when txs00 is empty, a transmission completion interrupt (intst00) is generated. figure 13-8. asynchronous serial interface transmission completion interrupt timing (a) stop bit length: 1 stop parity d7 d6 d2 d1 d0 start txd (output) intst00 (b) stop bit length: 2 stop parity d7 d6 d2 d1 d0 start txd (output) intst00 caution do not rewrite asynchronous serial interface mode register 00 (asim00) during a transmit operation. if asim00 is rewritten during transmission, subsequent transmission may not operate correctly (the normal state is restored by reset input). whether transmission is in progress or not can be judged by software using a transmission completion interrupt (intst00) or the interrupt request flag (stif00) set by intst00. chapter 13 serial interface 00 194 user ? s manual u13952ej3v0ud (d) reception when bit 6 (rxe00) of asynchronous serial interface mode register 00 (asim00) is set (1), a receive operation is enabled and sampling of the rxd pin input is performed. rxd pin input sampling is performed using the serial clock specified by asim00. when the rxd pin input becomes low, the 3-bit counter starts counting, and when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output. if the rxd pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 3-bit counter is initialized and starts counting, and data sampling is performed. when character data, a parity bit and one stop bit are detected after the start bit, reception of one frame of data ends. when one frame of data has been received, the receive data in the shift register is transferred to receive buffer register 00 (rxb00), and a reception completion interrupt (intsr00) is generated. if an error occurs, the receive data in which the error occurred is still transferred to rxb00, and intsr00 is generated. if the rxe00 bit is reset (0) during the receive operation, the receive operation is stopped immediately. in this case, the contents of rxb00 and asynchronous serial interface status register 00 (asis00) are not changed, and intsr00 is not generated. figure 13-9. asynchronous serial interface reception completion interrupt timing stop parity d7 d6 d2 d1 d0 start rxd (input) intsr00 caution be sure to read receive buffer register 00 (rxb00) even if a receive error occurs. if rxb00 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. chapter 13 serial interface 00 user ? s manual u13952ej3v0ud 195 (e) receive errors the following three errors may occur during a receive operation: a parity error, framing error, or overrun error. the data reception result error flag is set in asynchronous serial interface status register 00 (asis00). receive error causes are shown in table 13-7. what kind of error occurred during reception can be judged by reading the contents of asis00 in the receive error interrupt servicing (see figures 13-9 and 13-10 ). the contents of asis00 are reset (0) by reading receive buffer register 00 (rxb00) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). table 13-7. receive error causes receive errors cause parity error the parity specified at transmission and the reception data parity do not match. framing error a stop bit is not detected. overrun error reception of the next data is completed before data is read from the receive buffer register. figure 13-10. receive error timing (a) parity error occurs stop parity d7 d6 d2 d1 d0 start rxd (input) intsr00 (b) framing error or overrun error occurs stop parity d7 d6 d2 d1 d0 start rxd (input) intsr00 cautions 1. the contents of the asis00 register are reset (0) by reading receive buffer register 00 (rxb00) or receiving the next data. to ascertain the error contents, read asis00 before reading rxb00. 2. be sure to read receive buffer register 00 (rxb00) even if a receive error occurs. if rxb00 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. chapter 13 serial interface 00 196 user ? s manual u13952ej3v0ud (f) reading receive data when the reception completion interrupt (intsr00) is generated, receive data can be read by reading the value of receive buffer register 00 (rxb00). to read the receive data stored in receive buffer register 00 (rxb00), read while reception is enabled (rxe00 = 1). remark however, if it is necessary to read receive data after reception has stopped (rxe00 = 0), read using either of the following methods. (a) read after setting rxe00 = 0 after waiting for one cycle or more of the source clock selected by brgc00. (b) read after bit 2 (dir00) of serial operation mode register 00 (csim00) is set (1). program example of (a) (brgc00 = 00h (source clock = fx/2)) intrxe: ; chapter 13 serial interface 00 user ? s manual u13952ej3v0ud 197 (3) cautions on uart mode (a) when bit 7 (txe00) of asynchronous serial interface mode register 00 (asim00) is cleared during transmission, be sure to set transmit shift register 00 (txs00) to ffh, then set the txe00 bit to 1 before executing the next transmission. (b) when bit 6 (rxe00) of asynchronous serial interface mode register 00 (asim00) is cleared during reception, receive buffer register 00 (rxb00) and the reception completion interrupt (intsr00) are as follows. parity rxd pin rxb00 intsr00 <3> <1> <2> when rxe00 is set to 0 at the timing indicated by <1>, rxb00 holds the previous data and does not generate intsr00. when rxe00 is set to 0 at the timing indicated by <2>, rxb00 renews the data and does not generate intsr00. when rxe00 is set to 0 at the timing indicated by <3>, rxb00 renews the data and generates intsr00. chapter 13 serial interface 00 198 user?s manual u13952ej3v0ud 13.4.3 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connection of peripheral i/os and display controllers, etc., which incorporate a conventional synchronous serial interface, such as the 75xl series, 78k series, and 17k series. communication is performed using three lines: the serial clock (sck), serial output (so), and serial input (si). (1) register setting 3-wire serial i/o mode settings are performed using serial operation mode register 00 (csim00), asynchronous serial interface mode register 00 (asim00), and baud rate generator control register 00 (brgc00). (a) serial operation mode register 00 (csim00) csim00 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets csim00 to 00h. csie00 0 1 operation control in 3-wire serial i/o mode csie00 0000 dir00 csck00 0 csim00 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation stopped operation enabled dir00 0 1 start bit specification msb lsb csck00 0 1 clock selection in 3-wire serial i/o mode clock input to sck pin from external dedicated baud rate generator output caution bits 0 and 3 to 6 must be fixed to 0. chapter 13 serial interface 00 user ? s manual u13952ej3v0ud 199 (b) asynchronous serial interface mode register 00 (asim00) asim00 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets asim00 to 00h. asim00 must be set to 00h in the 3-wire serial i/o mode. txe00 0 1 transmit operation control txe00 rxe00 ps001 ps000 cl00 sl00 0 0 asim00 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe00 0 1 0 1 0 0 0 1 0 1 1 1 no parity 0 parity always added at transmission parity check is not performed at reception (no parity error occurs.) odd parity even parity receive operation control ps001 parity bit specification ps000 cl00 0 1 sl00 character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification cautions 1. bits 0 and 1 must be fixed to 0. 2. switching operation modes must be performed after the serial transmit/receive operation is stopped. chapter 13 serial interface 00 200 user ? s manual u13952ej3v0ud (c) baud rate generator control register 00 (brgc00) brgc00 is set using an 8-bit memory manipulation instruction. reset input sets brgc00 to 00h. tps003 0 0 0 0 0 0 0 0 tps003 tps002 tps001 tps000 0000 brgc00 r/w ff73h 00h r/w 76543210 tps002 0 0 0 0 1 1 1 1 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) tps001 0 0 1 1 0 0 1 1 tps000 0 1 0 1 0 1 0 1 n 1 2 3 4 5 6 7 8 setting prohibited symbol address after reset 3-bit counter source clock selection other than above cautions 1. when brgc00 is written during a communication operation, the output of the baud rate generator is disrupted and communications cannot be performed normally. be sure not to write to brgc00 during a communication operation. 2. do not select n = 1 during f x = 5.0 mhz operation because the baud rate rating is exceeded. remarks 1. f x : main system clock oscillation frequency 2. n: value in the above table that is determined in the settings of tps000 to tps003 (1 n 8) 3. the parenthesized values apply to operation at f x = 5.0 mhz. if the internal clock is used as the serial clock for the 3-wire serial i/o mode, set the tps000 to tps003 bits to set the frequency of the serial clock. to obtain the frequency to be set, use the following formula. when the serial clock is input from off-chip, setting brgc00 is unnecessary. serial clock frequency = [hz] f x : main system clock oscillation frequency n: value in the above table that is determined in the settings of tps000 to tps003 (1 n 8) f x 2 n + 1 chapter 13 serial interface 00 user ? s manual u13952ej3v0ud 201 (2) communication operation in the 3-wire serial i/o mode, data transmission/reception is performed in 8-bit units. data is transmitted/received bit by bit in synchronization with the serial clock. transmit shift register 00 (txs00/sio00) and receive shift register 00 (rxs00) shift operations are performed in synchronization with the fall of the serial clock (sck). then transmit data is held in the so latch and output from the so pin. also, receive data input to the si pin is latched in receive buffer register 00 (rxb00/sio00) on the rise of sck. at the end of an 8-bit transfer, the operation of txs00/sio00 or rxs00 stops automatically, and the interrupt request signal (intcsi00) is generated. figure 13-11. 3-wire serial i/o mode timing 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 end of transfer transfer start at the falling edge of sck sck si so intcsi00 (3) transfer start serial transfer is started by setting transfer data to transmit shift register 00 (txs00/sio00) when the following two conditions are satisfied. ? bit 7 (csie00) of serial operation mode register 00 (csim00) = 1 ? internal serial clock is stopped or sck is a high level after 8-bit serial transfer. caution if csie00 is set to 1 after data is written to txs00/sio00, transfer does not start. termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal (intcsi00). user?s manual u13952ej3v0ud 202 chapter 14 lcd controller/driver 14.1 functions of lcd controller/driver the functions of the lcd controller/driver of the pd789407a and 789417a subseries are as follows. (1) automatic output of segment and common signals based on automatic display data memory read (2) five different display modes: static 1/2 duty (1/2 bias) 1/3 duty (1/2 bias) 1/3 duty (1/3 bias) 1/4 duty (1/3 bias) (3) four different frame frequencies, selectable in each display mode (4) up to 28 segment signal outputs (s0 to s27) and four common signal outputs (com0 to com3) of these segment signal outputs, 12 outputs can be switched to i/o ports in 2-output units (p80/s27 to p87/s20 and p90/s19 to p93/s16). (5) voltage divider resistors (for lcd drive voltage generation) that a port itself can contain if so specified with a mask option (6) operation with a subsystem clock table 14-1 lists the maximum number of pixels that can be displayed in each display mode. table 14-1. maximum number of pixels bias mode number of time slices common signals used maximum number of pixels ? static com0 (com1 to com3) 28 (28 segment signals, 1 common signal) note 1 1/2 2 com0, com1 56 (28 segment signals, 2 common signals) note 2 3 com0 to com2 84 (28 segment signals, 3 common signals) note 3 1/3 3 com0 to com2 4 com0 to com3 112 (28 segment signals, 4 common signals) note 4 notes 1. three-digit lcd panel, each digit having an 8-segment configuration. 2. seven-digit lcd panel, each digit having a 4-segment configuration. 3. nine-digit lcd panel, each digit having a 3-segment configuration. 4. fourteen-digit lcd panel, each digit having a 2-segment configuration. chapter 14 lcd controller/driver user?s manual u13952ej3v0ud 203 14.2 configuration of lcd controller/driver the lcd controller/driver consists of the following hardware. table 14-2. configuration of lcd controller/driver item configuration display outputs 28 segment signals (16 dedicated segment signals and 12 segment and i/o port signals) 4 common signals (com0 to com3) control registers lcd display mode register 0 (lcdm0) lcd port selector 0 (lps0) lcd clock control register 0 (lcdc0) chapter 14 lcd controller/driver 204 user?s manual u13952ej3v0ud internal bus lcd clock control register 0 (lcdc0) lcdc03 lcdc02 lcdc01 lcdc00 2 2 lcd display mode register 0 (lcdm0) lcd port selector 0 (lps0) 3 selector prescaler segment selector lcd clock selector selector selector selector lcd drive voltage controller common driver lcdcl f lcd f lcd 2 6 f lcd 2 7 f lcd 2 8 f lcd 2 9 lps05 lcdon0 vaon0 lips0 lcdm02 lcdm01 lcdm00 lps04 lps03 lps02 lps01 lps00 6 v lc2 s /p8 v lc1 v lc0 bias p8 output buffer segment driver segment driver segment driver p9 output buffer com0 com1 com2 com3 3210 3210 65 74 f h display data memory lcdon s /p9 3210 3210 65 74 f h lcdon 3210 3210 65 74 f h p8 output latch lcdon s p9 output latch timing controller f x /2 3 f x /2 5 f x /2 7 f xt figure 14-1. block diagram of lcd controller/driver chapter 14 lcd controller/driver user ? s manual u13952ej3v0ud 205 14.3 registers controlling lcd controller/driver the following three registers are used to control the lcd controller/driver. lcd display mode register 0 (lcdm0) lcd port selector 0 (lps0) lcd clock control register 0 (lcdc0) (1) lcd display mode register 0 (lcdm0) lcdm0 specifies whether to enable display operation. it also specifies the operation mode, lcd drive power supply, and display mode. lcdm0 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets lcdm0 to 00h. figure 14-2. format of lcd display mode register 0 lcdon0 vaon0 0 lips0 0 lcdm02 lcdm01 lcdm00 lcdm0 symbol address after reset r/w ffb0h 00h r/w 76543210 lcd controller/driver display mode selection lcdm02 0 0 0 0 1 4 3 2 3 static setting prohibited lcdm01 0 0 1 1 0 lcdm00 0 1 0 1 0 control of lcd display lcdon0 0 1 display off (all segment outputs are deselected.) display on lcd drive power supply selection lips0 0 1 lcd controller/driver operation mode note vaon0 0 1 normal operation low-voltage operation lcd drive power is not supplied. lcd drive power is supplied to the bias pin. number of time slices bias mode 1/3 1/3 1/2 1/2 other than above note when the lcd display panel is not used, vaon0 and lips0 must be fixed to 0 to conserve power. caution before attempting to manipulate vaon0, set lips0 and lcdon0 to 0 to turn off the lcd. chapter 14 lcd controller/driver 206 user ? s manual u13952ej3v0ud (2) lcd port selector 0 (lps0) lps0 controls port and segment signal output switching. lps0 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets lps0 to 00h. figure 14-3. format of lcd port selector 0 cautions 1. bits 6 and 7 must be fixed to 0. 2. be sure to use segments in sequence from the smallest segment value (lps05 lps04 ? lps00). remark m = 8 n = 0 to 7 m = 9 n = 0 to 3 = 16 to 27 0 lps00 lps0 symbol address after reset r/w ffb1h 00h r/w 76543210 0 1 used as ports (pmn) lps04 lps03 lps02 lps01 lps00 p93/s16, p92/s17 p91/s18, p90/s19 p87/s20, p86/s21 p85/s22, p84/s23 p83/s24, p82/s25 p81/s26, p80/s27 used as segments (s ) lps05 lps01 lps02 lps04 lps05 0 lps03 chapter 14 lcd controller/driver user ? s manual u13952ej3v0ud 207 (3) lcd clock control register 0 (lcdc0) lcdc0 specifies the lcd source clock and lcd clock. the frame frequency is determined according to the lcd clock and the number of time slices. lcdc0 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets lcdc0 to 00h. figure 14-4. format of lcd clock control register 0 lcdc03 lcdc02 lcdc01 lcdc00 lcdc0 symbol address after reset r/w ffb2h 00h r/w 76543210 selection of lcd source clock frequency (f lcd ) note lcdc03 0 0 1 1 lcdc02 0 1 0 1 selection of lcd clock (lcdcl) frequency lcdc01 0 0 1 1 lcdc00 0 1 0 1 0000 f lcd /2 6 f lcd /2 7 f lcd /2 8 f lcd /2 9 f x /2 7 (39.1 khz) f xt (32.768 khz) f x /2 5 (156.3 khz) f x /2 3 (625 khz) note specify an lcd source clock (f lcd ) frequency of at least 32 khz. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. for example, table 14-3 lists the frame frequencies used when f xt (32.768 khz) is supplied to the lcd source clock (f lcd ). table 14-3. frame frequencies (hz) lcd clock (lcdcl) frequency number of time slices f xt /2 9 (64 hz) f xt /2 8 (128 hz) f xt /2 7 (256 hz) f xt /2 6 (512 hz) static 64 128 256 512 2 32 64 128 256 3 21 43 85 171 4 16 32 64 128 chapter 14 lcd controller/driver 208 user ? s manual u13952ej3v0ud 14.4 setting lcd controller/driver set the lcd controller/driver using the following procedure. <1> set the initial values in the lcd display data memory (fa00h to fa1bh). <2> set the pins to be used for segment output in lcd port selector 0 (lps0). <3> set the display and operation modes in lcd display mode register 0 (lcdm0). <4> set the lcd clock in lcd clock control register 0 (lcdc0). subsequent to this procedure, set the data to be displayed in the data memory. 14.5 lcd display data memory the lcd display data memory is mapped at addresses fa00h to fa1bh. data in the lcd display data memory can be displayed on the lcd panel using the lcd controller/driver. figure 14-5 shows the relationship between the contents of the lcd display data memory and the segment/common outputs. the part of the display data memory not used for display can be used as ordinary ram. figure 14-5. relationship between lcd display data memory contents and segment/common outputs s0 fa00h s1 fa01h s2 fa02h s3 fa03h s25/p82 fa09h s26/p81 fa1ah s27/p80 fa1bh com3 com2 com1 com0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 address caution no memory is allocated to the higher 4 bits of the lcd display data memory. be sure to fix there bits to 0. chapter 14 lcd controller/driver user ? s manual u13952ej3v0ud 209 14.6 common and segment signals each pixel of the lcd panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (lcd drive voltage, v lcd ). the pixels turn off when the potential difference becomes lower than v lcd . applying dc voltage to the common and segment signals of an lcd panel causes deterioration. to avoid this problem, this lcd panel is driven by ac voltage. (1) common signals each common signal is selected sequentially according to a specified number of time slices at the timing listed in table 14-4. in the static display mode, the same signal is output to com0 to com3. in the two-time-slice mode, leave the com2 and com3 pins open. in the three-time-slice mode, leave the com3 pin open. table 14-4. com signals com0 com1 com2 com3 com signal number of time slices static display mode two-time-slice mode three-time-slice mode four-time-slice mode open open open (2) segment signals the segment signals correspond to 28 bytes of lcd display data memory (fa00h to fa1bh). bits 0, 1, 2, and 3 of each byte are read in synchronization with com0, com1, com2, and com3, respectively. if a bit is 1, it is converted to the select voltage, and if it is 0, it is converted to the deselect voltage. the conversion results are output to the segment pins (s0 to s27). note that s16 to s27 can also be used as i/o port pins. check, with the information given above, what combination of front-surface electrodes (corresponding to the segment signals) and rear-surface electrodes (corresponding to the common signals) forms display patterns in the lcd display data memory, and write the bit data that corresponds to the desired display pattern on a one-to-one basis. lcd display data memory bits 1 and 2, bits 2 and 3, and bit 3 are not used for lcd display in the static display, two-time slot, and three-time slot modes, respectively. so these bits can be used for purposes other than display. lcd display data memory bits 4 to 7 are fixed to 0. chapter 14 lcd controller/driver 210 user ? s manual u13952ej3v0ud (3) output waveforms of common and segment signals the voltages listed in table 14-5 are output as common and segment signals. when both common and segment signals are at the select voltage, a display on-voltage of v lcd is obtained. the other combinations of the signals correspond to the display off-voltage. table 14-5. lcd drive voltage (a) static display mode segment signal select signal level deselect signal level common signal v ss0 /v lc0 v lc0 /v ss0 v lc0 /v ss0 ? v lcd /+v lcd 0 v/0 v (b) 1/2 bias method segment signal select signal level deselect signal level common signal v ss0 /v lc0 v lc0 /v ss0 select signal level v lc0 /v ss0 ? v lcd /+v lcd 0 v/0 v deselect signal level v lc1 = v lc2 ? v lcd /+ v lcd + v lcd / ? v lcd (c) 1/3 bias method segment signal select signal level deselect signal level common signal v ss0 /v lc0 v lc1 /v lc2 select signal level v lc0 /v ss0 ? v lcd /+v lcd ? v lcd /+ v lcd deselect signal level v lc2 /v lc1 ? v lcd /+ v lcd ? v lcd /+ v lcd 1 2 1 2 1 2 1 2 1 3 1 3 1 3 1 3 1 3 1 3 chapter 14 lcd controller/driver user ? s manual u13952ej3v0ud 211 figure 14-6 shows the common signal waveforms, and figure 14-7 shows the voltages and phases of the common and segment signals. figure 14-6. common signal waveforms (a) static display mode comn (static display) t f = t v lc0 v ss0 v lcd t: one lcd clock period t f : frame frequency (b) 1/2 bias method comn (two-time slot mode) t f = 2 t v lc0 v ss0 v lcd v lc2 comn (three-time slot mode) t f = 3 t v lc0 v ss0 v lcd v lc2 t: one lcd clock period t f : frame frequency (c) 1/3 bias method comn (three-time slot mode) t f = 3 t v lc0 v ss0 v lcd v lc1 v lc2 t f = 4 t comn (four-time slot mode) v lc0 v lcd v lc1 v lc2 v ss0 t: one lcd clock period t f : frame frequency chapter 14 lcd controller/driver 212 user ? s manual u13952ej3v0ud figure 14-7. voltages and phases of common and segment signals (a) static display mode select deselect common signal segment signal v lc0 v ss0 v lcd v lc0 v ss0 v lcd tt t: one lcd clock period (b) 1/2 bias method select deselect common signal segment signal v lc0 v ss0 v lcd v lc0 v ss0 v lcd tt v lc2 v lc2 t: one lcd clock period (c) 1/3 bias method select deselect common signal segment signal v lc0 v ss0 v lcd v lc0 v ss0 v lcd tt v lc2 v lc2 v lc1 v lc1 t: one lcd clock period chapter 14 lcd controller/driver user ? s manual u13952ej3v0ud 213 14.7 supplying lcd drive voltages v lc0 , v lc1 , and v lc2 the mask rom versions (except the pd78f9418a) of the lcd display can incorporate voltage divider resistors for generating lcd drive power as specified using a mask option. incorporating voltage divider resistors can generate lcd drive voltages that meet each bias method listed in table 14-6, without using external voltage divider resistors. the lcd drive voltage can be supplied to the bias pin to support various lcd drive voltage levels. table 14-6. lcd drive voltages (with on-chip voltage divider resistors) bias method no bias (static) 1/2 bias method 1/3 bias method lcd drive voltage pin v lc0 v lcd v lcd v lcd v lc1 v lcd v lcd note v lcd v lc2 v lcd v lcd note for the 1/2 bias method, it is necessary to connect the v lc1 and v lc2 pins externally. remarks 1. if the bias and v lc0 pins are open, v lcd = v dd (if voltage divider resistors are included). 2. if the bias and v lc0 pins are connected, v lcd = v dd . figure 14-8 shows examples of generating lcd drive voltages internally according to table 14-6. 2 3 2 3 1 2 1 3 1 3 3 5 chapter 14 lcd controller/driver 214 user ? s manual u13952ej3v0ud figure 14-8. examples of lcd drive power connections (with on-chip voltage divider resistors) (a) 1/3 bias method and static display mode (v dd = 5 v and v lcd = 3 v) (b) 1/2 bias method (v dd = 5 v and v lcd = 5 v) lips0 v lc0 v dd p-ch bias pin 2 r r r r v lc1 v lc2 v lcd v lcd = 3/5 v dd v ss v ss0 lips0 v lc0 v dd p-ch bias pin 2 r r r r v lc1 v lc2 v lcd v lcd = v dd v ss v ss0 (c) 1/3 bias method and static display mode (v dd = 5 v and v lcd = 5 v) lips0 v lc0 v dd p-ch bias pin 2 r r r r v lc1 v lc2 v lcd v lcd = v dd v ss v ss0 lips0: bit 4 of lcd display mode register 0 (lcdm0) chapter 14 lcd controller/driver user?s manual u13952ej3v0ud 215 14.8 display modes 14.8.1 static display example figure 14-10 shows how the three-digit lcd panel having the display pattern shown in figure 14-9 is connected to the segment signals (s0 to s23) and the common signal (com0) of the pd789407a or 789417a subseries chip. this example displays data "12.3" in the lcd panel. the contents of the display data memory (addresses fa00h to fa17h) correspond to this display. the following description focuses on numeral "2." ( ) displayed in the second digit. to display "2." in the lcd panel, it is necessary to apply the select or deselect voltage to the s8 to s15 pins according to table 14-7 at the timing of the common signal com0; see figure 14-9 for the relationship between the segment signals and lcd segments. table 14-7. select and deselect voltages (com0) segment s8 s9 s10 s11 s12 s13 s14 s15 common com0 select deselect select select deselect select select select according to table 14-7, it is determined that the bit-0 pattern of the display data memory locations (fa08h to fa0fh) must be 10110111. figure 14-11 shows the lcd drive waveforms of s11 and s12, and com0. when the select voltage is applied to s11 at the timing of com0, an alternate rectangle waveform, +v lcd / ? v lcd , is generated to turn on the corresponding lcd segment. com1 to com3 are supplied with the same waveform as for com0. so, com0 to com3 may be connected together to increase the driving capacity. figure 14-9. static lcd display pattern and electrode connections s 8n+3 s 8n+2 s 8n+5 s 8n+1 s 8n s 8n+4 s 8n+6 s 8n+7 com0 remark n = 0 to 2 chapter 14 lcd controller/driver 216 user ? s manual u13952ej3v0ud figure 14-10. example of connecting static lcd panel 000001101110110110101110 bit 0 bit 1 bit 2 bit 3 timing strobe data memory address lcd panel fa00h 1 2 3 4 5 6 7 8 9 a b c d e f fa10h 1 2 3 4 5 6 7 s 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s 15 s 16 s 17 s 18 s 19 s 20 s 21 s 22 s 23 com 3 can be connected together com 2 com 1 com 0 chapter 14 lcd controller/driver user ? s manual u13952ej3v0ud 217 figure 14-11. static lcd drive waveform examples t f v lc0 v ss0 com0 v lc0 v ss0 s11 v lc0 v ss0 s12 +v lcd 0 com0 to s12 ? v lcd +v lcd 0 com0 to s11 ? v lcd chapter 14 lcd controller/driver 218 user ? s manual u13952ej3v0ud 14.8.2 two-time-slice display example figure 14-13 shows how the seven-digit lcd panel having the display pattern shown in figure 14-12 is connected to the segment signals (s0 to s27) and the common signals (com0 and com1) of the pd789407a or 789417a subseries chip. this example displays data "123456.7" in the lcd panel. the contents of the display data memory (addresses fa00h to fa1bh) correspond to this display. the following description focuses on numeral "3" ( ) displayed in the fifth digit. to display "3" in the lcd panel, it is necessary to apply the select or deselect voltage to the s16 to s19 pins according to table 14-8 at the timing of the common signals com0 and com1; see figure 14-12 for the relationship between the segment signals and lcd segments. table 14-8. select and deselect voltages (com0 and com1) segment s16 s17 s18 s19 common com0 select select deselect deselect com1 deselect select select select according to table 14-8, it is determined that the display data memory location (fa13h) that corresponds to s19 must contain xx10. figure 14-14 shows examples of lcd drive waveforms between the s19 signal and each common signal. when the select voltage is applied to s19 at the timing of com1, an alternate rectangle waveform, +v lcd / ? v lcd , is generated to turn on the corresponding lcd segment. figure 14-12. two-time-slice lcd display pattern and electrode connections s 4n+2 s 4n+3 s 4n+1 s 4n com0 com1 remark n = 0 to 6 chapter 14 lcd controller/driver user ? s manual u13952ej3v0ud 219 figure 14-13. example of connecting two-time-slice lcd panel : can always be used to store any data because the two-time-slice mode is being used. 0011101000110111010111010111 0000111011100010111011110100 bit 0 bit 1 bit 2 bit 3 timing strobe data memory address lcd panel fa00h 1 2 3 4 5 6 7 8 9 a b c d e f fa10h 1 2 3 4 5 6 7 8 9 a b s 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s 15 s 16 s 17 s 18 s 19 s 20 s 21 s 22 s 23 s 24 s 25 s 26 s 27 com 3 com 2 com 1 com 0 open open chapter 14 lcd controller/driver 220 user ? s manual u13952ej3v0ud figure 14-14. two-time-slice lcd drive waveform examples (1/2 bias method) t f v lc0 v ss0 com0 v lc0 v ss0 v lc0 v ss0 s19 +v lcd 0 com1 to s19 ? v lcd +v lcd 0 com0 to s19 ? v lcd v lc1,2 v lc1,2 v lc1,2 com1 +1/2v lcd +1/2v lcd ? 1/2v lcd ? 1/2v lcd chapter 14 lcd controller/driver user ? s manual u13952ej3v0ud 221 14.8.3 three-time-slice display example figure 14-16 shows how the nine-digit lcd panel having the display pattern shown in figure 14-15 is connected to the segment signals (s0 to s26) and the common signals (com0 to com2) of the pd789407a or 789417a subseries chip. this example displays data "123456.789" in the lcd panel. the contents of the display data memory (addresses fa00h to fa1ah) correspond to this display. the following description focuses on numeral "6." ( ) displayed in the fourth digit. to display "6." in the lcd panel, it is necessary to apply the select or deselect voltage to the s9 to s11 pins according to table 14-9 at the timing of the common signals com0 to com2; see figure 14-15 for the relationship between the segment signals and lcd segments. table 14-9. select and deselect voltages (com0 to com2) segment s9 s10 s11 common com0 deselect select select com1 select select select com2 select select ? according to table 14-9, it is determined that the display data memory location (fa09h) that corresponds to s9 must contain x110. figures 14-17 and 14-18 show examples of lcd drive waveforms between the s9 signal and each common signal in the 1/2 and 1/3 bias methods, respectively. when the select voltage is applied to s9 at the timing of com1 or com2, an alternate rectangle waveform, +v lcd / ? v lcd , is generated to turn on the corresponding lcd segment. figure 14-15. three-time-slice lcd display pattern and electrode connections s 3n+2 s 3n com0 com2 s 3n+1 com1 remark n = 0 to 8 chapter 14 lcd controller/driver 222 user ? s manual u13952ej3v0ud figure 14-16. example of connecting three-time-slice lcd panel x ? : can be used to store any data because there is no corresponding segment in the lcd panel. : can always be used to store any data because the three-time-slice mode is being used. 001011011101110110111111111 001110011011011111001111011 00 10 10 00 10 11 00 10 00 bit 0 bit 1 bit 2 bit 3 timing strobe data memory address lcd panel fa00h 1 2 3 4 5 6 7 8 9 a b c d e f fa10h 1 2 3 4 5 6 7 8 9 a s 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s 15 s 16 s 17 s 18 s 19 s 20 s 21 s 22 s 23 s 24 s 25 s 26 com 3 com 2 com 1 com 0 open x ? x ? x ? x ? x ? x ? x ? x ? x ? chapter 14 lcd controller/driver user ? s manual u13952ej3v0ud 223 figure 14-17. three-time-slice lcd drive waveform examples (1/2 bias method) t f v lc0 v ss0 com0 v lc0 v ss0 v lc0 v ss0 com2 +v lcd 0 com1 to s9 ? v lcd +v lcd 0 com0 to s9 ? v lcd v lc1,2 v lc1,2 v lc1,2 com1 +1/2v lcd +1/2v lcd ? 1/2v lcd ? 1/2v lcd v lc0 v ss0 s9 v lc1,2 +v lcd 0 com2 to s9 ? v lcd +1/2v lcd ? 1/2v lcd chapter 14 lcd controller/driver 224 user ? s manual u13952ej3v0ud figure 14-18. three-time-slice lcd drive waveform examples (1/3 bias method) v lc0 v lc2 com0 +v lcd 0 com0 to s9 ? v lcd v lc1 +1/3v lcd ? 1/3v lcd v ss0 v lc0 v lc2 com1 v lc1 v ss0 v lc0 v lc2 com2 v lc1 v ss0 v lc0 v lc2 s9 v lc1 v ss0 +v lcd 0 com1 to s9 ? v lcd +1/3v lcd ? 1/3v lcd +v lcd 0 com2 to s9 ? v lcd +1/3v lcd ? 1/3v lcd t f chapter 14 lcd controller/driver user ? s manual u13952ej3v0ud 225 14.8.4 four-time-slice display example figure 14-20 shows how the 14-digit lcd panel having the display pattern shown in figure 14-19 is connected to the segment signals (s0 to s27) and the common signals (com0 to com3) of the pd789407a or 789417a subseries chip. this example displays data "123456.78901234" in the lcd panel. the contents of the display data memory (addresses fa00h to fa1bh) correspond to this display. the following description focuses on numeral "6." ( ) displayed in the ninth digit. to display "6." in the lcd panel, it is necessary to apply the select or deselect voltage to the s16 and s17 pins according to table 14-10 at the timing of the common signals com0 to com3; see figure 14-19 for the relationship between the segment signals and lcd segments. table 14-10. select and deselect voltages (com0 to com3) segment s16 s17 common com0 select select com1 deselect select com2 select select com3 select select according to table 14-10, it is determined that the display data memory location (fa16h) that corresponds to s16 must contain 1101. figure 14-21 shows examples of lcd drive waveforms between the s16 signal and each common signal. when the select voltage is applied to s16 at the timing of com0, an alternate rectangle waveform, +v lcd / ? v lcd , is generated to turn on the corresponding lcd segment. figure 14-19. four-time-slice lcd display pattern and electrode connections remark n = 0 to 13 com0 s 2n com1 s 2n+1 com2 com3 chapter 14 lcd controller/driver 226 user ? s manual u13952ej3v0ud figure 14-20. example of connecting four-time-slice lcd panel 0001011011111111111100010110 0111111110100111110101111111 0110010101110111011101100101 0010100010110010001000101000 bit 0 bit 1 bit 2 bit 3 timing strobe data memory address lcd panel fa00h 1 2 3 4 5 6 7 8 9 a b c d e f fa10h 1 2 3 4 5 6 7 8 9 a b s 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s 15 s 16 s 17 s 18 s 19 s 20 s 21 s 22 s 23 s 24 s 25 s 26 s 27 com 3 com 2 com 1 com 0 chapter 14 lcd controller/driver user ? s manual u13952ej3v0ud 227 figure 14-21. four-time-slice lcd drive waveform examples (1/3 bias method) t f v lc0 v lc2 com0 +v lcd 0 com0 to s16 ? v lcd v lc1 +1/3v lcd ? 1/3v lcd v ss0 v lc0 v lc2 com1 v lc1 v ss0 v lc0 v lc2 com2 v lc1 v ss0 v lc0 v lc2 com3 v lc1 v ss0 +v lcd 0 com1 to s16 ? v lcd +1/3v lcd ? 1/3v lcd v lc0 v lc2 s16 v lc1 v ss0 remark the waveforms for com2 to s16 and com3 to s16 are omitted. user?s manual u13952ej3v0ud 228 chapter 15 interrupt functions 15.1 interrupt function types the following two types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally. it does not undergo interrupt priority control and is given top priority over all other interrupt requests. a standby release signal is generated. one interrupt source from the watchdog timer is incorporated as a non-maskable interrupt. (2) maskable interrupt these interrupts undergo mask control. if two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority as shown in table 15-1. a standby release signal is generated. five external interrupt and 11 internal interrupt sources are incorporated as maskable interrupts. 15.2 interrupt sources and configuration a total of 17 non-maskable and maskable interrupts are incorporated as interrupt sources (see table 15-1 ). chapter 15 interrupt functions user?s manual u13952ej3v0ud 229 table 15-1. interrupt source list interrupt type priority note 1 interrupt source internal/ external vector table basic configuration name trigger address type note 2 non-maskable ? intwdt watchdog timer overflow (with watchdog timer mode 1 selected) internal 0004h (a) maskable 0 intwdt watchdog timer overflow (with interval timer mode selected) (b) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intsr00 end of serial interface 00 uart reception internal 000eh intcsi00 end of serial interface 00 3-wire sio transfer reception 6 intst00 end of serial interface 00 uart transmission 0010h 7 intwt watch timer interrupt 0012h 8 intwti interval timer interrupt 0014h 9 inttm00 generation of matching signal of 8-bit timer/event counter 00 0016h 10 inttm01 generation of matching signal of 8-bit timer/event counter 01 0018h 11 inttm02 generation of matching signal of 8-bit timer 02 001ah 12 inttm50 generation of matching signal of 16-bit timer 50 001ch (b) 13 intkr00 key return signal detection external 001eh (c) 14 intad0 a/d conversion completion signal internal 0020h 15 intcmp0 comparator signal 0022h (b) notes 1. ?priority? is the priority order when several maskable interrupts are generated at the same time. 0 is the highest and 15 is the lowest. 2. basic configuration types (a) to (c) correspond to (a) to (c) in figure 15-1. chapter 15 interrupt functions 230 user?s manual u13952ej3v0ud figure 15-1. basic configuration of interrupt function (a) internal non-maskable interrupt internal bus interrupt request vector table address generator standby release signal (b) internal maskable interrupt mk if ie internal bus interrupt request vector table address generator standby release signal (c) external maskable interrupt mk if ie internal bus external interrupt mode register (intm0, intm1) interrupt request edge detector vector table address generator standby release signal if: interrupt request flag ie: interrupt enable flag mk: interrupt mask flag chapter 15 interrupt functions user ? s manual u13952ej3v0ud 231 15.3 registers controlling interrupt function the following five registers are used to control the interrupt functions. ? interrupt request flag registers 0, 1 (if0 and if1) ? interrupt mask flag registers 0, 1 (mk0 and mk1) ? external interrupt mode registers 0, 1 (intm0 and intm1) ? program status word (psw) ? key return mode register 00 (krm00) table 15-2 lists the interrupt request flag and interrupt mask flag names corresponding to interrupt requests. table 15-2. flags corresponding to interrupt request signal name interrupt request signal name interrupt request flag interrupt mask flag intwdt intp0 intp1 intp2 intp3 intsr00/intcsi00 intst00 intwt intwti inttm00 inttm01 inttm02 inttm50 intkr00 intad0 intcmp0 tmif4 pif0 pif1 pif2 pif3 srif00 stif00 wtif wtiif tmif00 tmif01 tmif02 tmif50 krif00 adif0 cmpif0 tmmk4 pmk0 pmk1 pmk2 pmk3 srmk00 stmk00 wtmk wtimk tmmk00 tmmk01 tmmk02 tmmk50 krmk00 admk0 cmpmk0 chapter 15 interrupt functions 232 user ? s manual u13952ej3v0ud (1) interrupt request flag registers 0, 1 (if0 and if1) the interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. it is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset input. if0 and if1 are set using a 1-bit or 8-bit memory manipulation instruction. reset input sets if0 and if1 to 00h. figure 15-2. format of interrupt request flag register 0 1 cmpif0 adif0 krif00 tmif50 tmif02 tmif01 tmif00 wtiif if1 ffe1h 00h r/w interrupt request flag no interrupt request signal is generated interrupt request signal is generated; interrupt request state xxifx <6> <5> <4> <3> <2> <1> <7> <0> wtif stif00 srif00 pif3 pif2 pif1 pif0 tmif4 if0 r/w ffe0h 00h r/w symbol address after reset <6> <5> <4> <3> <2> <1> <7> <0> cautions 1. the tmif4 flag is r/w enabled only when the watchdog timer is used as an interval timer. if watchdog timer mode 1 or 2 is used, set the tmif4 flag to 0. 2. because port 2 has an alternate function as an external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode. 3. if an interrupt is acknowledged, the interrupt request flag is automatically cleared before the interrupt routine is entered. chapter 15 interrupt functions user ? s manual u13952ej3v0ud 233 (2) interrupt mask flag registers 0, 1 (mk0 and mk1) the interrupt mask flag is used to enable/disable the corresponding maskable interrupt service. mk0 and mk1 are set using a 1-bit or 8-bit memory manipulation instruction. reset input sets mk0 and mk1 to ffh. figure 15-3. format of interrupt mask flag register 0 1 cmpmk0 admk0 krmk00 tmmk50 tmmk02 tmmk01 tmmk00 wtimk mk1 ffe5h ffh r/w interrupt servicing control interrupt servicing enabled interrupt servicing disabled <6> <5> <4> <3> <2> <1> <7> <0> xxmkx wtmk stmk00 srmk00 pmk3 pmk2 pmk1 pmk0 tmmk4 mk0 r/w ffe4h ffh r/w symbol address after reset <6> <5> <4> <3> <2> <1> <7> <0> cautions 1. if the tmmk4 flag is read when the watchdog timer is used in watchdog timer mode 1 or 2, its value becomes undefined. 2. because port 2 has an alternate function as an external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode. chapter 15 interrupt functions 234 user ? s manual u13952ej3v0ud (3) external interrupt mode register 0 (intm0) this register is used to specify a valid edge for intp0 to intp2. intm0 is set using an 8-bit memory manipulation instruction. reset input sets intm0 to 00h. figure 15-4. format of external interrupt mode register 0 0 0 1 1 es21 es20 es11 es10 es01 es00 0 0 intm0 r/w ffech 00h r/w 76543210 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 symbol address after reset intp0 valid edge selection falling edge rising edge setting prohibited both rising and falling edges intp1 valid edge selection falling edge rising edge setting prohibited both rising and falling edges intp2 valid edge selection falling edge rising edge setting prohibited both rising and falling edges es00 es01 es11 es10 es20 es21 cautions 1. bits 0 and 1 must be fixed to 0. 2. before setting the intm0 register, be sure to set xxmkx of the relevant interrupt mask flag to 1 to disable interrupts. after that, clear the interrupt mask flag (xxmkx = 0) to enable interrupts after clearing the interrupt request flag (xxifx = 0). chapter 15 interrupt functions user ? s manual u13952ej3v0ud 235 (4) external interrupt mode register 1 (intm1) intm1 is used to specify a valid edge for intp3 and intcmp0. intm1 is set using an 8-bit memory manipulation instruction. reset input sets intm1 to 00h. figure 15-5. format of external interrupt mode register 1 es61 es60 0000 es31 es30 intm1 76543210 es31 0 0 1 1 intp3 valid edge selection es30 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges es61 0 0 1 1 intcmp0 valid edge selection es60 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges symbol address after reset r/w ffedh 00h r/w cautions 1. bits 2 to 5 must be fixed to 0. 2. before setting intm1, set the corresponding interrupt mask flag register to 1 to disable interrupts. after that, clear (0) the corresponding interrupt request flag to enable interrupts, then clear the corresponding interrupt mask flag register. chapter 15 interrupt functions 236 user ? s manual u13952ej3v0ud (5) program status word (psw) the program status word is a register used to hold the instruction execution result and the current status for interrupt requests. the ie flag to set maskable interrupt enable/disable is mapped to the psw. besides 8-bit unit read/write, this register can carry out operations via bit manipulation instructions and dedicated instructions (ei, di). when a vectored interrupt is acknowledged, the psw is automatically saved into a stack, and the ie flag is reset to 0. reset input sets the psw to 02h. figure 15-6. configuration of program status word ie z 0 ac 0 0 1 cy psw 76543210 ie 0 1 02h symbol after reset used when normal instruction is executed interrupt acknowledge enable/disable disabled enabled chapter 15 interrupt functions user?s manual u13952ej3v0ud 237 (6) key return mode register 00 (krm00) this register sets the pin that detects a key return signal (falling edge of port 4). krm00 is set using a 1-bit or 8-bit memory manipulation instruction. bit 0 (krm000) is set in 4-bit units for kr0/p40 to kr3/p43 pins. bits 4 and 5 (krm004 and krm005) are set in 1-bit units for kr4/p44 and kr5/p45 pins, respectively. reset input sets krm00 to 00h. figures 15-7 and 15-8 show the format of key return mode register 00 and the block diagram of the falling edge detector, respectively. figure 15-7. format of key return mode register 00 0 1 00 krm005 krm004 000 krm000 krm00 fff5h 00h r/w address after reset r/w key return signal detection selection no detection detection (detecting falling edge of port 4) 654321 70 krm00n symbol cautions 1. bits 1 to 3, 6, and 7 must be fixed to 0. 2. when the krm00 register is set to 1, a pull-up resistor is connected automatically. however, the pull-up resistor is cut if the pin is in output mode. 3. before setting krm00, always set bit 5 of mk1 (krmk00 = 1) to disable interrupts in advance. after setting krm00, clear bit 5 of mk1 (krmk00 = 0) after clearing bit 5 of if1 (krif00 = 0) to enable interrupts. 4. the key return signal cannot be detected while even one of the pins that specify detection of the key return signal is low, even if a falling edge is generated at other key return pins. remark n = 0, 4, 5 figure 15-8. block diagram of falling edge detector p40/kr0 p41/kr1 p42/kr2 p43/kr3 p44/kr4 p45/kr5 falling edge detector krmk krif00 set signal standby release signal key return mode register 00 (krm00) note selector note selector that selects the pin used for falling edge input chapter 15 interrupt functions 238 user ? s manual u13952ej3v0ud 15.4 operation of interrupt servicing 15.4.1 non-maskable interrupt acknowledgment operation the non-maskable interrupt is unconditionally acknowledged even when interrupts are disabled. it is not subject to interrupt priority control and takes precedence over all other interrupts. when the non-maskable interrupt request is acknowledged, the psw and pc are saved to the stack in that order, the ie flag is reset to 0, the contents of the vector table are loaded to the pc, and then program execution branches. caution during non-maskable interrupt servicing program execution, do not input another non- maskable interrupt request; if it is input, the servicing program will be interrupted and the new non-maskable interrupt request will be acknowledged. chapter 15 interrupt functions user ? s manual u13952ej3v0ud 239 figure 15-9. flowchart of non-maskable interrupt request acknowledgment start wdtm4 = 1 (watchdog timer mode is selected) interval timer no wdt overflows no yes reset processing no yes yes interrupt request is generated interrupt servicing is started wdtm3 = 0 (non-maskable interrupt is selected) wdtm: watchdog timer mode register wdt: watchdog timer figure 15-10. timing of non-maskable interrupt request acknowledgment instruction instruction saving psw and pc, and jump to interrupt servicing interrupt servicing program cpu processing tmif4 figure 15-11. non-maskable interrupt request acknowledgment second interrupt servicing first interrupt servicing nmi request (second) nmi request (first) main routine chapter 15 interrupt functions 240 user ? s manual u13952ej3v0ud 15.4.2 maskable interrupt acknowledgment operation a maskable interrupt can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. a vectored interrupt is acknowledged in the interrupt enabled status (when the ie flag is set to 1). the time required to start the interrupt servicing after a maskable interrupt request has been generated is as follows: table 15-3. time from generation of maskable interrupt request to servicing minimum time maximum time note 9 clocks 19 clocks note the wait time is maximum when an interrupt request is generated immediately before the bt or bf instruction. remark 1 clock: (f cpu : cpu clock) when two or more maskable interrupt requests are generated at the same time, they are acknowledged starting from the one assigned the highest priority by the priority specification flag. an interrupt held pending is acknowledged when the status in which it can be acknowledged is set. figure 15-12 shows the algorithm of acknowledging interrupts. when a maskable interrupt request is acknowledged, the psw and pc are saved to the stack in that order, the ie flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the pc, and execution branches. to restore from interrupt servicing, use the reti instruction. figure 15-12. interrupt acknowledgment program algorithm start xxif = 1 ? xxmk = 0 ? ie = 1 ? vectored interrupt servicing yes (interrupt request generated) yes yes no no no interrupt request pending interrupt request pending 1 f cpu chapter 15 interrupt functions user ? s manual u13952ej3v0ud 241 figure 15-13. interrupt request acknowledgment timing (example: mov a, r) clock cpu mov a, r saving psw and pc, and jump to interrupt servicing 8 clocks interrupt servicing program interrupt request if the interrupt request has generated an interrupt request flag (xxif) by the time the instruction clocks under execution, n clocks (n = 4 to 10), are n ? 1, interrupt request acknowledgment processing will start following the completion of the instruction under execution. figure 15-13 shows an example using the 8-bit data transfer instruction mov a, r. because this instruction is executed in 4 clocks, if an interrupt request is generated between the start of execution and the 3rd clock, interrupt request acknowledgment processing will take place following the completion of mov a, r. figure 15-14. interrupt request acknowledgment timing (when interrupt request flag is generated in final clock under execution) clock cpu nop mov a, r saving psw and pc, and jump to interrupt servicing interrupt servicing program interrupt request 8 clocks if the interrupt request flag (xxif) is generated in the final clock of the instruction, interrupt request acknowledgment processing will begin after execution of the next instruction is complete. figure 15-14 shows an example whereby an interrupt request was generated in the 2nd clock of nop (a 2-clock instruction). in this case, the interrupt request will be processed after execution of mov a, r, which follows nop, is complete. caution when interrupt request flag registers 0 and 1 (if0 and if1) or interrupt mask flag registers 0 and 1 (mk0 and mk1) are being accessed, interrupt requests will be held pending. 15.4.3 multiple interrupt servicing processing in which another interrupt request is acknowledged while an interrupt request is serviced is called multiple interrupt servicing. multiple interrupts are not performed unless an interrupt request is enabled (ie = 1) (except non-maskable interrupt request). the other interrupt request is disabled (ie = 0) at the time when an interrupt request is acknowledged. therefore, it is necessary to set (1) the ie flag to realize the interrupt enable state using an ei instruction during interrupt request servicing in order to enable multiple interrupt servicing. chapter 15 interrupt functions 242 user ? s manual u13952ej3v0ud figure 15-15. example of multiple interrupt example 1. acknowledging multiple interrupts intyy ei main processing ei intyy processing intxx processing reti ie = 0 intxx reti ie = 0 the interrupt request intyy is acknowledged and multiple interrupts are performed during the interrupt intxx processing. before each interrupt request is acknowledged, the ei instruction is issued and the interrupt request is enabled. example 2. multiple interrupts are not performed because interrupts are disabled intyy ei main processing reti intyy processing intxx processing ie = 0 intxx reti intyy is held pending ie = 0 interrupt requests are disabled (the ei instruction is not issued) in the interrupt intxx processing. the interrupt request intyy is not acknowledged and multiple interrupts are not performed. intyy is held pending and is acknowledged after intxx servicing is completed. ie = 0: interrupt request disabled chapter 15 interrupt functions user ? s manual u13952ej3v0ud 243 15.4.4 putting interrupt requests on hold if an interrupt (such as a maskable, non-maskable, or external interrupt) is requested when a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. such instructions include: ? instructions that manipulate interrupt request flag registers 0, 1 (if0 and if1) ? instructions that manipulate interrupt mask flag registers 0, 1 (mk0 and mk1) user?s manual u13952ej3v0ud 244 chapter 16 standby function 16.1 standby function and configuration 16.1.1 standby function the standby function is used to reduce the power consumption of the system and can be effected in the following two modes: (1) halt mode this mode is set when the halt instruction is executed. the halt mode stops the operation clock of the cpu. the system clock oscillator continues oscillating. this mode does not reduce the power consumption as much as the stop mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations. (2) stop mode this mode is set when the stop instruction is executed. the stop mode stops the main system clock oscillator and stops the entire system. the power consumption of the cpu can be substantially reduced in this mode. the data memory can be retained at the low voltage (v dd = 1.8 v). therefore, this mode is useful for retaining the contents of the data memory at an extremely low current. the stop mode can be released by an interrupt request, so that this mode can be used for intermittent operation. however, some time is required until the system clock oscillator stabilizes after the stop mode has been released. if processing must be resumed immediately by using an interrupt request, therefore, use the halt mode. in both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are all retained. in addition, the statuses of the output latch of the i/o ports and output buffer are also retained. caution to set the stop mode, be sure to stop the operations of the peripheral hardware, and then execute the stop instruction. chapter 16 standby function user?s manual u13952ej3v0ud 245 16.1.2 standby function control register the wait time after the stop mode is released upon interrupt request until oscillation stabilizes is controlled by the oscillation stabilization time selection register (osts). osts is set using an 8-bit memory manipulation instruction. reset input sets osts to 04h. however, it takes 2 15 /f x , not 2 17 /f x , until the stop mode is released by reset input. figure 16-1. format of oscillation stabilization time selection register osts2 0 0 1 00000 osts2 osts1 osts0 osts r/w fffah 04h r/w 76543210 osts1 0 1 0 2 12 /f x 2 15 /f x 2 17 /f x (819 s) (6.55 ms) (26.2 ms) osts0 0 0 0 setting prohibited symbol address after reset oscillation stabilization time selection other than above caution the wait time after the stop mode is released does not include the time from stop mode release to clock oscillation start (?a? in the figure below), regardless of release by reset input or by interrupt generation. v ss0 , v ss1 a stop mode release x1 pin voltage waveform remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. chapter 16 standby function 246 user ? s manual u13952ej3v0ud 16.2 operation of standby function 16.2.1 halt mode (1) halt mode the halt mode is set by executing the halt instruction. the operation status in the halt mode is shown in the following table. table 16-1. halt mode operating status item halt mode operation status while main system clock is running halt mode operation status while subsystem clock is r unning while the subsystem clock is running while the subsystem clock is not running while the main system clock is running while the main system clock is not running main system clock generator oscillation enabled does not run. cpu operation stopped port (output latch) remains in the state existing before the selection of halt mode. 16-bit timer (tm50) operation enabled operation stopped 8-bit timer/event counters (tm00 and tm01) operation enabled operation enabled note 1 8-bit timer (tm02) operation enabled operation enabled note 2 operation enabled operation enabled note 3 watch timer operation enabled operation enabled note 2 operation enabled operation enabled note 3 watchdog timer operation enabled operation stopped serial interface operation enabled operation enabled note 4 a/d converter operation stopped lcd controller/driver operation enabled operation enabled note 2 operation enabled operation enabled note 3 comparator operation enabled note 5 external interrupt operation enabled note 6 notes 1. operation is enabled only when ti0 or ti1 is selected as the count clock. 2. operation is enabled while the main system clock is selected. 3. operation is enabled while the subsystem clock is selected. 4. operation is enabled in both 3-wire serial i/o and uart modes while an external clock is being used. 5. operation is enabled while tm02 is operating, or as an external interrupt. 6. maskable interrupt that is not masked chapter 16 standby function user ? s manual u13952ej3v0ud 247 (2) releasing halt mode the halt mode can be released by the following three types of sources: (a) releasing by unmasked interrupt request the halt mode is released by an unmasked interrupt request. in this case, if interrupts are enabled to be acknowledged, vectored interrupt servicing is performed. if interrupts are disabled, the instruction at the next address is executed. figure 16-2. releasing halt mode by interrupt halt instruction standby release signal wait wait halt mode operation mode operation mode clock oscillation remarks 1. the broken lines indicate the case where the interrupt request that has released the standby mode is acknowledged. 2. the wait time is as follows: ? when vectored interrupt servicing is performed: 9 to 10 clocks ? when vectored interrupt servicing is not performed: 1 to 2 clocks (b) releasing by non-maskable interrupt request the halt mode is released regardless of whether interrupts are enabled or disabled, and vectored interrupt servicing is performed. chapter 16 standby function 248 user ? s manual u13952ej3v0ud (c) releasing by reset input when the halt mode is released by the reset signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. figure 16-3. releasing halt mode by reset input halt instruction reset signal wait (2 15 /f x : 6.55 ms) reset period halt mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. table 16-2. operation after release of halt mode releasing source mkxx ie operation maskable interrupt request 0 0 executes next address instruction 0 1 executes interrupt servicing 1 x retains halt mode non-maskable interrupt request ? x executes interrupt servicing reset input - ? - ? reset processing x: don ? t care chapter 16 standby function user ? s manual u13952ej3v0ud 249 16.2.2 stop mode (1) setting and operation status of stop mode the stop mode is set by executing the stop instruction. caution because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. when the stop mode is set, therefore, the halt mode is set immediately after the stop instruction has been executed, the wait time set by the oscillation stabilization time selection register (osts) elapses, and then an operation mode is set. the operation status in the stop mode is shown in the following table. table 16-3. stop mode operating status item stop mode operation status while main system clock is running while the subsystem clock is r unning while the sub system clock is not r unning main system clock generator osc illation stopped cpu operation stopped port (output latch) remains in the state existing before the selection of stop mode. 16-bit timer (tm50) operation stopped 8-bit timer/event counter (tm00 and tm01) operation enabled note 1 8-bit timer (tm02) operation enabled note 2 operation stopped watch timer operation enabled note 2 operation stopped watchdog timer operation stopped serial interface operation enabled note 3 a/d converter operation stopped lcd controller/driver operation enabled note 2 operation stopped comparator operation enabled notes 5, 6 operation enabled note 6 external interrupt operation enabled note 4 notes 1. operation is enabled only when ti0 or ti1 is selected as the count clock. 2. operation is enabled while the subsystem clock is selected. 3. operation is enabled in both 3-wire serial i/o and uart modes while an external clock is being used. 4. maskable interrupt that is not masked 5. operation is enabled while tm02 is running. 6. operation is enabled as an external interrupt. chapter 16 standby function 250 user ? s manual u13952ej3v0ud (2) releasing stop mode the stop mode can be released by the following two types of sources: (a) releasing by unmasked interrupt request the stop mode can be released by an unmasked interrupt request. in this case, if interrupts are enabled to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization time has elapsed. if interrupts are disabled, the instruction at the next address is executed. figure 16-4. releasing stop mode by interrupt stop instruction standby release signal wait (set time by osts) stop mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation remark the broken lines indicate the case where the interrupt request that has released the standby mode is acknowledged. chapter 16 standby function user ? s manual u13952ej3v0ud 251 (b) releasing by reset input when the stop mode is released by the reset signal, the reset operation is performed after the oscillation stabilization time has elapsed. figure 16-5. releasing stop mode by reset input stop instruction reset signal wait (2 15 /f x : 6.55 ms) stop mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation reset period remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. table 16-4. operation after release of stop mode releasing source mkxx ie operation maskable interrupt request 0 0 executes next address instruction 0 1 executes interrupt servicing 1 x retains stop mode reset input ? - ? - reset processing x: don ? t care user?s manual u13952ej3v0ud 252 chapter 17 reset function the following two operations are available to generate reset signals. (1) external reset input via reset pin (2) internal reset by program loop time detected by the watchdog timer the external and internal resets have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h by reset input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware item is set to the status shown in table 17-1. each pin is high impedance during reset input or during the oscillation stabilization time just after reset release. when a high level is input to the reset pin, the reset is released and program execution is started after the oscillation stabilization time (2 15 /fx) has elapsed. the reset applied by the watchdog timer overflow is automatically released after reset, and program execution is started after the oscillation stabilization time (2 15 /fx) has elapsed (see figures 17-2 through 17-4 ). cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. when the stop mode is released by reset, the stop mode contents are held during reset input. however, the port pins become high impedance. figure 17-1. block diagram of reset function reset interrupt function count clock reset controller watchdog timer over- flow reset signal stop chapter 17 r eset f unction user ? s manual u13952ej3v0ud 253 figure 17-2. reset timing by reset input x1 reset internal reset signal port pin during normal operation delay delay hi-z reset period (oscillation stops) normal operation (reset processing) oscillation stabilization time wait figure 17-3. reset timing by overflow in watchdog timer x1 overflow in watchdog timer internal reset signal port pin hi-z during normal operation reset period (oscillation continues) normal operation (reset processing) oscillation stabilization time wait figure 17-4. reset timing by reset input in stop mode x1 reset internal reset signal port pin delay delay hi-z stop instruction execution during normal operation reset period (oscillation stops) stop status (oscillation stops) normal operation (reset processing) oscillation stabilization time wait chapter 17 r eset f unction 254 user ? s manual u13952ej3v0ud table 17-1. hardware status after reset (1/2) hardware status after reset program counter (pc) note 1 the contents of reset vector tables (0000h and 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h ram data memory undefined note 2 general-purpose registers undefined note 2 ports (p0, p2, p4, p5, p8, and p9) (output latch) 00h port mode registers (pm0, pm2, pm4, pm5, pm8, and pm9) ffh pull-up resistor option registers (pu0 to pu2) 00h processor clock control register (pcc) 02h suboscillation mode register (sckm) 00h subclock control register (css) 00h oscillation stabilization time selection register (osts) 04h 16-bit timer timer counter (tm50) 0000h compare register (cr50) ffffh capture register (tcp50) undefined mode control register (tmc50) 00h 8-bit timer/event counter timer counters (tm00, tm01, and tm02) 00h compare registers (cr00, cr01, and cr02) undefined mode control registers (tmc00, tmc01, and tmc02) 00h watch timer mode control register (wtm) 00h watchdog timer timer clock selection register (tcl2) 00h mode register (wdtm) 00h a/d converter mode register (adm0) 00h a/d input selection register (ads0) 00h a/d conversion result register (adcr0) undefined comparator mode register (cmprm0) 00h notes 1. during reset input and oscillation stabilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware remains unchanged after reset. 2. the post-reset values are retained in the standby mode. chapter 17 r eset f unction user ? s manual u13952ej3v0ud 255 table 17-1. hardware status after reset (2/2) hardware status after reset mode register (csim00) 00h asynchronous serial interface mode register (asim00) 00h asynchronous serial interface status register (asis00) 00h baud rate generator control register (brgc00) 00h transmit shift register (txs00) ffh serial interface receive buffer register (rxb00) undefined lcd display mode register (lcdm0) 00h lcd port selector (lps0) 00h lcd controller/driver lcd clock control register (lcdc0) 00h request flag registers (if0 and if1) 00h mask flag registers (mk0 and mk1) ffh external interrupt mode registers (intm0 and intm1) 00h interrupts key return mode register (krm00) 00h user?s manual u13952ej3v0ud 256 chapter 18 pd78f9418a the pd78f9418a is a version with the internal rom of the mask rom version replaced by flash memory. the differences between the pd78f9418a and the mask rom versions are shown in table 18-1. table 18-1. differences between pd78f9418a and mask rom versions flash memory version mask rom version item pd78f9418a pd789405a pd789415a pd789406a pd789416a pd789407a pd789417a rom 32 kb (flash memory) 12 kb 16 kb 24 kb high-speed ram 512 bytes internal memory lcd data ram 28 bytes pull-up resistor 32 (software control only) 36 (software control: 32, mask option control: 4) divider resistor for lcd driving not provided can be specified on-chip by mask option ic pin not provided provided v pp pin provided not provided electrical specifications refer to chapter 21 electrical specifications . cautions 1. there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom version. 2. when a/d conversion result register 0 (adcr0) is used as the 8-bit a/d converter ( pd789407a subseries), adcr0 will be manipulated by an 8-bit memory manipulation instruction. when used as the 10-bit a/d converter ( pd789417a subseries), adcr0 will be manipulated by a 16-bit memory manipulation instruction. however, when the pd78f9418a is used as the flash memory version of the pd789405a, 789406a, and 789407a, adcr0 can be manipulated by an 8-bit memory manipulation instruction. in this case, use the object file assembled in the pd789405a, 789406a, and 789407a. chapter 18 pd78f9418a user?s manual u13952ej3v0ud 257 18.1 flash memory characteristics flash memory programming is performed by connecting a dedicated flash programmer (flashpro iii (part no. fl- pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)) to the target system with the pd78f9418a mounted on the target system (on-board). a flash memory program adapter (fa adapter), which is a target board used exclusively for programming, is also provided. remark fl-pr3, fl-pr4, and the program adapter are products made by naito densei machida mfg. co., ltd. (tel +81-45-475-4191). programming using flash memory has the following advantages. ? software can be modified after the microcontroller is solder-mounted on the target system. ? distinguishing software facilities small-quantity, varied model production ? easy data adjustment when starting mass production 18.1.1 programming environment the following shows the environment required for pd78f9418a flash memory programming. when flashpro iii (part no. fl-pr3, pg-fp3) or flashpro iv (part no. fl-pr4, pg-fp4) is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. communication between the host machine and flash programmer is performed via rs-232c/usb (rev. 1.1). for details, refer to the manuals for flashpro iii/flashpro iv. remark usb is supported by flashpro iv only. figure 18-1. environment for writing program to flash memory host machine rs-232c usb dedicated flash programmer pd78f9418a v pp v dd v ss reset 3-wire serial i/o, uart or pseudo 3-wire chapter 18 pd78f9418a 258 user ? s manual u13952ej3v0ud 18.1.2 communication mode use the communication mode shown in table 18-2 to perform communication between the dedicated flash programmer and pd78f9418a. table 18-2. communication mode list type setting note 1 cpu clock communication mode comm port sio clock in flashpro on target board multiple rate pins used number of v pp pulses 3-wire serial i/o sio ch-0 (3-wire, sync.) 100 hz to 1.25 mhz note 2 1, 2, 4, 5 mhz notes 2, 3 1 to 5 mhz note 2 1.0 si/rxd/p22 so/txd/p21 sck/asck/p20 0 uart uart ch-0 (async.) 4,800 to 76,800 bps notes 2, 4 5 mhz note 5 4.91 or 5 mhz note 2 1.0 rxd/si/p22 txd/so/p21 8 port a (pseudo- 3 wire) p01 p02 p00 12 pseudo 3-wire port b (pseudo- 3 wire) 100 hz to 1 khz 1, 2, 4, 5 mhz notes 2, 3 1 to 5 mhz note 2 1.0 p40/kr0 p41/kr1 p42/kr2 13 notes 1. selection items for type settings on the dedicated flash programmer (flashpro iii (part no. fl-pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)). 2. the possible setting range differs depending on the voltage. for details, refer to chapter 21 electrical specifications . 3. 2 or 4 mhz only for flashpro iii 4. because signal wave slew also affects uart communication, in addition to the baud rate error, thoroughly evaluate the slew and baud rate error. 5. only for flashpro iv. however, when using flashpro iii, be sure to select the clock of the resonator on the board. uart cannot be used with the clock supplied by flashpro iii. figure 18-2. communication mode selection format 10 v v ss v dd v pp v dd v ss reset 12 n v pp pulses chapter 18 pd78f9418a user ? s manual u13952ej3v0ud 259 figure 18-3. example of connection with dedicated flash programmer (a) 3-wire serial i/o dedicated flash programmer vpp1 vdd reset sck so si clk note 1 gnd v pp v dd0 , v dd1 reset sck si so x1 v ss0 , v ss1 pd78f9418a (b) uart dedicated flash programmer vpp1 vdd reset so si clk notes 1, 2 gnd v pp v dd0 , v dd1 reset r x d t x d x1 v ss0 , v ss1 pd78f9418a (c) pseudo 3-wire (when p0 is used) dedicated flash programmer vpp1 vdd reset sck so si gnd v pp v dd0 , v dd1 reset p00 (serial clock) p02 (serial input) p01 (serial output) clk note 1 x1 v ss0 , v ss1 pd78f9418a notes 1. connect this pin when the system clock is supplied from the dedicated flash programmer. if a resonator is already connected to the x1 pin, do not connect to the clk pin. 2. when using uart with flashpro iii, the clock of the resonator connected to the x1 pin must be used, so do not connect to the clk pin. caution the v dd pin, if already connected to the power supply, must be connected to the vdd pin of the dedicated flash programmer. when using the power supply connected to the v dd pin, supply voltage before starting programming. chapter 18 pd78f9418a 260 user ? s manual u13952ej3v0ud if flashpro iii (part no. fl-pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4) is used as a dedicated flash programmer, the following signals are generated for the pd78f9418a. for details, refer to the manual of flashpro iii/flashpro iv. table 18-3. pin connection list signal name i/o pin function pin name 3-wire serial i/o uart ps eudo 3-wire vpp1 output write voltage v pp vpp2 ?? ? vdd i/o v dd voltage generation/ voltage monitoring v dd0 , v dd1 note note note gnd ? ground v ss0 , v ss1 clk output clock output x1 reset output reset signal reset si input receive signal so/txd/p01/p41 so output transmit signal si/rxd/p02/p42 sck output transfer clock sck/p00/p40 hs input handshake signal ? note v dd voltage must be supplied before programming is started. remark : pin must be connected. : if the signal is supplied on the target board, pin does not need to be connected. : pin does not need to be connected. chapter 18 pd78f9418a user ? s manual u13952ej3v0ud 261 18.1.3 on-board pin connections when programming on the target system, provide a connector on the target system to connect to the dedicated flash programmer. there may be cases in which an on-board function that switches from the normal operation mode to flash memory programming mode is required. chapter 18 pd78f9418a 262 user ? s manual u13952ej3v0ud (1) signal conflict a signal conflict occurs if the dedicated flash programmer (output) is connected to a serial interface pin (input) connected to another device (output). to prevent this signal conflict, isolate the connection with the other device or put the other device in the output high impedance status. figure 18-5. signal conflict (serial interface input pin) pd78f9418a signal conflict output pin in the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict. to prevent this, isolate the signal on the device side. connection pin of dedicated flash programmer other device input pin (2) malfunction of another device when the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) connected to another device (input), a signal may be output to the device, causing a malfunction. to prevent such malfunction, isolate the connection with other device or set so that the input signal to the device is ignored. figure 18-6. malfunction of another device pd78f9418a input pin input pin pin pin other device other device connection pin of dedicated flash programmer connection pin of dedicated flash programmer if the signal output by the pd78f9418a affects another device in the flash memory programming mode, isolate the signal on the device side. if the signal output by the dedicated flash programmer affects another device, isolate the signal on the device side. pd78f9418a chapter 18 pd78f9418a user ? s manual u13952ej3v0ud 263 chapter 18 pd78f9418a 264 user ? s manual u13952ej3v0ud 18.1.4 connection when using flash memory writing adapter the following shows an example of the recommended connection when using the flash memory writing adapter. figure 18-8. example of flash memory writing adapter connection when using 3-wire serial i/o mode pd78f9418a gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 chapter 18 pd78f9418a user ? s manual u13952ej3v0ud 265 figure 18-9. example of flash memory writing adapter connection when using uart mode pd78f9418a gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 chapter 18 pd78f9418a 266 user ? s manual u13952ej3v0ud figure 18-10. example of flash memory writing adapter connection when using pseudo 3-wire mode (when p0 is used) pd78f9418a gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 user?s manual u13952ej3v0ud 267 chapter 19 mask options the mask rom versions of the pd789407a and pd789417a subseries have the following mask options. caution the flash memory version does not have a mask option. 19.1 mask option for pins table 19-1. selection of mask option for pins pin mask option p50 to p53 whether a pull-up resistor is to be incorporated can be specified in 1-bit units. for p50 to p53 (port 5), a mask option is used to specify whether a pull-up resistor is to be incorporated. the mask option is selectable in 1-bit units. 19.2 mask option for voltage division resistor for lcd driver a mask option is used to specify whether a voltage division resistor is to be incorporated for the lcd driver, as listed below: table 19-2. combination of selectable voltage division resistor r lc1 (2 r lc2 ) none 20 k ? 200 k ? r lc2 none { ?? 10 k ? { { ? 100 k ? { ? { { : selectable ? : not selectable lips0 lips0: bit 4 of lcd display mode register 0 (lcdm0) p-ch v dd v lc0 v lc1 v lcd v lc2 v ss r lc2 r lc2 r lc2 r lc1 bias user?s manual u13952ej3v0ud 268 chapter 20 instruction set this chapter lists the instruction set of the pd789407a and 789417a subseries. for details of the operation and machine language (instruction code) of each instruction, refer to 78k/0s series instructions user?s manual (u11047e) . 20.1 operation 20.1.1 operand identifiers and description methods operands are described in the operands column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). when there are two or more description methods, select one of them. uppercase letters and the symbols #, !, $, and [ ] are keywords and are described as they are. each symbol has the following meaning. ? #: immediate data specification ? $: relative address specification ? !: absolute address specification ? [ ]: indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $ and [ ] symbols. for operand register identifiers r and rp, either functional names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 20-1. operand identifiers and description methods identifier description method r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol saddr saddrp fe20h to ff1fh immediate data or label fe20h to ff1fh immediate data or label (even addresses only) addr16 addr5 0000h to ffffh immediate data or label (only even addresses for 16-bit data transfer instructions) 0040h to 007fh immediate data or label (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label remark see table 3-3 for symbols of special function registers. chapter 20 instruction set user?s manual u13952ej3v0ud 269 20.1.2 description of ?operation? column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag ie: interrupt request enable flag nmis: flag indicating non-maskable interrupt servicing in progress ( ): memory contents indicated by address or register contents in parenthesis x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) v : exclusive logical sum (exclusive or) : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 20.1.3 description of ?flag? column (blank): unchanged 0: cleared to 0 1: set to 1 x: set/cleared according to the result r: previously saved value is restored chapter 20 instruction set 270 user?s manual u13952ej3v0ud 20.2 operation list mnemonic operands bytes clocks operation flag zaccy mov r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte a, r note 1 24a r r, a note 1 24r a a, saddr 2 4 a (saddr) saddr, a 2 4 (saddr) a a, sfr 2 4 a sfr sfr, a 2 4 sfr a a, !addr16 3 8 a (addr16) !addr16, a 3 8 (addr16) a psw, #byte 3 6 psw byte x x x a, psw 2 4 a psw psw, a 2 4 psw axxx a, [de] 1 6 a (de) [de], a 1 6 (de) a a, [hl] 1 6 a (hl) [hl], a 1 6 (hl) a a, [hl+byte] 2 6 a (hl + byte) [hl+byte], a 2 6 (hl + byte) a xch a, x 1 4 a ? x a, r note 2 26a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? sfr a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) a, [hl+byte] 2 8 a ? (hl + byte) notes 1. except r = a. 2. except r = a, x. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). chapter 20 instruction set user?s manual u13952ej3v0ud 271 mnemonic operands bytes clocks operation flag zaccy movw rp, #word 3 6 rp word ax, saddrp 2 6 ax (saddrp) saddrp, ax 2 8 (saddrp) ax ax, rp note 1 4 ax rp rp, ax note 14rp ax xchw ax, rp note 1 8 ax ? rp add a, #byte 2 4 a, cy a + byte x x x saddr, #byte 3 6 (saddr), cy (saddr) + byte x x x a, r 2 4 a, cy a + r x x x a, saddr 2 4 a, cy a + (saddr) x x x a, !addr16 3 8 a, cy a + (addr16) x x x a, [hl] 1 6 a, cy a + (hl) x x x a, [hl+byte] 2 6 a, cy a + (hl + byte) x x x addc a, #byte 2 4 a, cy a + byte + cy x x x saddr, #byte 3 6 (saddr), cy (saddr) + byte + cy x x x a, r 2 4 a, cy a + r + cy x x x a, saddr 2 4 a, cy a + (saddr) + cy x x x a, !addr16 3 8 a, cy a + (addr16) + cy x x x a, [hl] 1 6 a, cy a + (hl) + cy x x x a, [hl+byte] 2 6 a, cy a + (hl + byte) + cy x x x sub a, #byte 2 4 a, cy a ? byte x x x saddr, #byte 3 6 (saddr), cy (saddr) ? byte x x x a, r 2 4 a, cy a ? rxxx a, saddr 2 4 a, cy a ? (saddr) x x x a, !addr16 3 8 a, cy a ? (addr16) x x x a, [hl] 1 6 a, cy a ? (hl) x x x a, [hl+byte] 2 6 a, cy a ? (hl + byte) x x x note only when rp = bc, de, or hl. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). chapter 20 instruction set 272 user?s manual u13952ej3v0ud mnemonic operands bytes clocks operation flag zaccy subc a, #byte 2 4 a, cy a ? byte ? cy x x x saddr, #byte 3 6 (saddr), cy (saddr) ? byte ? cy x x x a, r 2 4 a, cy a ? r ? cy x x x a, saddr 2 4 a, cy a ? (saddr) ? cy x x x a, !addr16 3 8 a, cy a ? (addr16) ? cy x x x a, [hl] 1 6 a, cy a ? (hl) ? cy x x x a, [hl+byte] 2 6 a, cy a ? (hl + byte) ? cy x x x and a, #byte 2 4 a a byte x saddr, #byte 3 6 (saddr) (saddr) byte x a, r 2 4 a a rx a, saddr 2 4 a a (saddr) x a, !addr16 3 8 a a (addr16) x a, [hl] 1 6 a a (hl) x a, [hl+byte] 2 6 a a (hl + byte) x or a, #byte 2 4 a a byte x saddr, #byte 3 6 (saddr) (saddr) byte x a, r 2 4 a a rx a, saddr 2 4 a a (saddr) x a, !addr16 3 8 a a (addr16) x a, [hl] 1 6 a a (hl) x a, [hl+byte] 2 6 a a (hl + byte) x xor a, #byte 2 4 a a v byte x saddr, #byte 3 6 (saddr) (saddr) v byte x a, r 2 4 a a v rx a, saddr 2 4 a a v (saddr) x a, !addr16 3 8 a a v (addr16) x a, [hl] 1 6 a a v (hl) x a, [hl+byte] 2 6 a a v (hl + byte) x remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). chapter 20 instruction set user?s manual u13952ej3v0ud 273 mnemonic operands bytes clocks operation flag zaccy cmp a, #byte 2 4 a ? byte x x x saddr, #byte 3 6 (saddr) ? byte x x x a, r 2 4 a ? rxxx a, saddr 2 4 a ? (saddr) x x x a, !addr16 3 8 a ? (addr16) x x x a, [hl] 1 6 a ? (hl) x x x a, [hl+byte] 2 6 a ? (hl + byte) x x x addw ax, #word 3 6 ax, cy ax + word x x x subw ax, #word 3 6 ax, cy ax ? word x x x cmpw ax, #word 3 6 ax ? word x x x inc r 2 4 r r + 1 x x saddr 2 4 (saddr) (saddr) + 1 x x dec r 2 4 r r ? 1xx saddr 2 4 (saddr) (saddr) ? 1xx incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ? 1 ror a, 1 1 2 (cy, a 7 a 0 , a m ? 1 a m ) 1x rol a, 1 1 2 (cy, a 0 a 7 , a m+1 a m ) 1x rorc a, 1 1 2 (cy a 0 , a 7 cy, a m ? 1 a m ) 1x rolc a, 1 1 2 (cy a 7 , a 0 cy, a m+1 a m ) 1x set1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 3 6 psw.bit 1xxx [hl].bit 2 10 (hl).bit 1 clr1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 3 6 psw.bit 0xxx [hl].bit 2 10 (hl).bit 0 set1 cy 1 2 cy 11 clr1 cy 1 2 cy 00 not1 cy 1 2 cy cy x remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). chapter 20 instruction set 274 user?s manual u13952ej3v0ud mnemonic operands bytes clocks operation flag zaccy call !addr16 3 6 (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callt [addr5] 1 8 (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 ret 1 6 pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 8 pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3, nmis 0 rrr push psw 1 2 (sp ? 1) psw, sp sp ? 1 rp 1 4 (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 pop psw 1 4 psw (sp), sp sp + 1 r r r rp 1 6 rp h (sp + 1), rp l (sp), sp sp + 2 movw sp, ax 2 8 sp ax ax, sp 2 6 ax sp br !addr16 3 6 pc addr16 $addr16 2 6 pc pc + 2 + jdisp8 ax 1 6 pc h a, pc l x bc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 1 bnc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 0 bt saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 1 bf saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 0 dbnz b, $addr16 2 6 b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ? 1, then pc pc + 2 + jdisp8 if c 0 saddr, $addr16 3 8 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 nop 1 2 no operation ei 3 6 ie 1 (enable interrupt) di 3 6 ie 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). chapter 20 instruction set user?s manual u13952ej3v0ud 275 20.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, inc, dec, ror, rol, rorc, rolc, push, pop, dbnz 2nd operand 1st operand #byte a r sfr saddr !addr16 psw [de] [hl] [hl+b y te] $addr16 1 none a add addc sub subc and or xor cmp mov note xch note add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc rmovmov inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov [hl+byte] mov note except r = a. chapter 20 instruction set 276 user?s manual u13952ej3v0ud (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand 1st operand #word ax rp note saddrp sp none ax addw subw cmpw movw xchw movw movw rp movw movw note incw decw push pop saddrp movw sp movw note only when rp = bc, de, or hl. (3) bit manipulation instructions set1, clr1, not1, bt, bf 2nd operand 1st operand $addr16 none a.bit bt bf set1 clr1 sfr.bit bt bf set1 clr1 saddr.bit bt bf set1 clr1 psw.bit bt bf set1 clr1 [hl].bit set1 clr1 cy set1 clr1 not1 chapter 20 instruction set user?s manual u13952ej3v0ud 277 (4) call instructions/branch instructions call, callt, br, bc, bnc, bz, bnz, dbnz 2nd operand 1st operand ax !addr16 [addr5] $addr16 basic instructions br call br callt br bc bnc bz bnz compound instructions dbnz (5) other instructions ret, reti, nop, ei, di, halt, stop user?s manual u13952ej3v0ud 278 chapter 21 electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd av dd av ref av dd ? 0.3 v v dd av dd + 0.3 v av ref v dd + 0.3 v av ref av dd + 0.3 v ? 0.3 to +6.5 v supply voltage v pp pd78f9418a only note ?0.3 to +10.5 v v i1 pins other than p50 to p53 ? 0.3 to v dd + 0.3 v input voltage v i2 p50 to p53 n-ch open drain ? 0.3 to +13 v output voltage v o ? 0.3 to v dd + 0.3 v 1 pin ? 10 ma output current, high i oh total for all pins ? 30 ma 1 pin 30 ma output current, low i ol total for all pins 160 ma in normal operation mode ? 40 to +85 c operating ambient temperature t a during flash memory programming 10 to 40 c mask rom version ?65 to +150 c storage temperature t stg pd78f9418a ?40 to +125 c note make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (1.8 v) of the operating voltage range (see a in the figure below). when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (1.8 v) of the operating voltage range of v dd (see b in the figure below). 1.8 v v dd 0 v 0 v v pp 1.8 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. chapter 21 electrical specifications user ? s manual u13952ej3v0ud 279 main system clock oscillator characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 v dd = oscillation voltage range 1.0 5.0 mhz ceramic resonator x2 x1 v ss0 c2 c1 oscillation stabilization time note 2 after v dd has reached min. of oscillation start voltage 4ms oscillation frequency (f x ) note 1 1.0 5.0 mhz v dd = 4.5 to 5.5 v 10 ms crystal resonator x2 x1 v ss0 c2 c1 oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 30 ms x1 input frequency (f x ) note 1 1.0 5.0 mhz x1 x2 x1 input high-/low-level widths (t xh , t xl ) 85 500 ns x1 input frequency (f x ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock x1 x2 open x1 input high-/low-level widths (t xh , t xl ) v dd = 2.7 to 5.5 v 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use a resonator whose oscillation is stabilized within the oscillation wait time. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? ? ? ? keep the wiring length as short as possible. ? ? ? ? do not cross the wiring with the other signal lines. ? ? ? ? do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss0 . ? ? ? ? do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. chapter 21 electrical specifications 280 user ? s manual u13952ej3v0ud subsystem clock oscillator characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz v dd = 4.5 to 5.5 v 1.2 2 s crystal resonator xt2 xt1 v ss0 c4 c3 r oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 10 s xt1 input frequency (f xt ) note 1 32 35 khz external clock xt1 xt2 xt1 input high-/low- level widths (t xth , t xtl ) 14.3 15.6 s notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use a resonator whose oscillation is stabilized within the oscillation wait time. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. ? ? ? ? keep the wiring length as short as possible. ? ? ? ? do not cross the wiring with the other signal lines. ? ? ? ? do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss0 . ? ? ? ? do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. chapter 21 electrical specifications user?s manual u13952ej3v0ud 281 dc characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 1.8 to 5.5 v) (1/3) parameter symbol conditions min. typ. max. unit per pin ? 1ma output current, high i oh total for all pins ? 15 ma per pin 10 ma output current, low i ol total for all pins 80 ma v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih1 p00 to p03, p46, p47, p60 to p66, p80 to p87, p90 to p93 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.7v dd 12 v n-ch open drain v dd = 1.8 to 5.5 v 0.9v dd 12 v v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih2 p50 to p53 on-chip pull-up resistor v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.8v dd v dd v v ih3 reset, p20 to p27, p40 to p45 v dd = 1.8 to 5.5 v 0.9v dd v dd v input voltage, high v ih4 x1, x2, xt1, xt2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il1 p00 to p03, p46, p47, p60 to p66, p80 to p87, p90 to p93 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il2 p50 to p53 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.2v dd v v il3 reset, p20 to p27, p40 to p45 v dd = 1.8 to 5.5 v 0 0.1v dd v input voltage, low v il4 x1, x2, xt1, xt2 v dd = 1.8 to 5.5 v 0 0.1 v i oh = ? 1 ma v dd = 4.5 to 5.5 v v dd ? 1.0 v output voltage, high v oh i oh = ? 100 av dd = 1.8 to 5.5 v v dd ? 0.5 v v dd = 4.5 to 5.5 v i ol = 10 ma 1.0 v v ol1 pins other than p50 to p53 v dd = 1.8 to 5.5 v i ol = 400 a 0.5 v v dd = 4.5 to 5.5 v i ol = 10 ma 1.0 v output voltage, low v ol2 p50 to p53 v dd = 1.8 to 5.5 v i ol = 1.6 ma 0.4 v i lih1 pins other than p50 to p53 (n-ch open drain), x1, x2, xt1, and xt2 3 a i lih2 v in = v dd x1, x2, xt1, xt2 20 a input leakage current, high i lih3 v in = 12 v p50 to p53 (n-ch open drain) 20 a i lil1 pins other than p50 to p53 (n-ch open drain), x1, x2, xt1, and xt2 ? 3 a i lil2 x1, x2, xt1, xt2 ? 20 a input leakage current, low i lil3 v in = 0 v p50 to p53 (n-ch open drain) ? 3 note a note a low-level input leakage current of ? 30 a (max.) flows only during the 1-cycle time after a read instruction is executed to p50 to p53 when on-chip pull-up resistors are not connected to p50 to p53 (specified by mask option) and p50 to p53 are set to input mode. at times other than this, a ? 3 a (max.) current flows. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. chapter 21 electrical specifications 282 user?s manual u13952ej3v0ud dc characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 1.8 to 5.5 v) (2/3) parameter symbol conditions min. typ. max. unit output leakage current, high i loh v out = v dd 3 a output leakage current, low i lol v out = 0 v ? 3 a software pull-up resistor r 1 v in = 0 v, pins other than p50 to p53 50 100 200 k ? mask option pull- up resistor note 1 r 2 v in = 0 v, p50 to p53 15 30 60 k ? v dd = 5.0 v 10% note 5 2.0 4.0 ma v dd = 3.0 v 10% note 6 0.6 1.2 ma i dd1 note 2 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 6 0.3 0.6 ma v dd = 5.0 v 10% note 5 1.1 2.2 ma v dd = 3.0 v 10% note 6 0.4 0.8 ma i dd2 note 2 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 6 0.2 0.4 ma v dd = 5.0 v 10% 30 90 a v dd = 3.0 v 10% 9 50 a i dd3 note 2 32.768 khz crystal oscillation operating mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 2.0 v 10% 4 25 a v dd = 5.0 v 10% 25 55 a v dd = 3.0 v 10% 5 25 a i dd4 note 2 32.768 khz crystal oscillation halt mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 2.0 v 10% 2.5 12.5 a v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5.0 a t a = 25 c 0.05 3.0 a i dd5 note 2 32.768 khz crystal oscillation stop mode v dd = 2.0 v 10% 0.05 3.0 a v dd = 5.0 v 10% 2.6 6.0 ma v dd = 3.0 v 10% 1.2 3.6 ma supply current (mask rom version) i dd6 note 3 5.0 mhz crystal oscillation a/d operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% 0.9 2.7 ma notes 1. mask rom version only 2. the current flowing to av ref (a/d operation on (adcs0 = 1)), av dd current, and the port current (including the current flowing through the on-chip pull-up resistors) is not included. 3. the current flowing to av ref (a/d operation on (adcs0 = 1)) and the port current (including the current flowing through the on-chip pull-up resistors) is not included. for the current flowing to av ref , refer to the parameter of ?resistance between av ref and av ss ? in the 8-bit a/d converter characteristics and 10-bit a/d converter characteristics . 4. when the main system clock is stopped 5. high-speed mode operation (when processor clock control register (pcc) is set to 00h) 6. low-speed mode operation (when pcc is set to 02h) remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. chapter 21 electrical specifications user?s manual u13952ej3v0ud 283 dc characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 1.8 to 5.5 v) (3/3) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% note 4 5.0 14.0 ma v dd = 3.0 v 10% note 5 2.0 5.0 ma i dd1 note 1 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 1.5 3.0 ma v dd = 5.0 v 10% note 4 2.0 6.0 ma v dd = 3.0 v 10% note 5 1.0 3.0 ma i dd2 note 1 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 0.7 2.0 ma v dd = 5.0 v 10% 200 600 a v dd = 3.0 v 10% 150 450 a i dd3 note 1 32.768 khz crystal oscillation operating mode note 3 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 2.0 v 10% 100 300 a v dd = 5.0 v 10% 50 150 a v dd = 3.0 v 10% 30 90 a i dd4 note 1 32.768 khz crystal oscillation halt mode note 3 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 2.0 v 10% 20 60 a v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5.0 a t a = 25 c 0.05 3.0 a i dd5 note 1 32.768 khz crystal oscillation stop mode v dd = 2.0 v 10% 0.05 3.0 a v dd = 5.0 v 10% note 4 6.0 16.0 ma v dd = 3.0 v 10% note 5 3.0 7.0 ma supply current ( pd78f9418a) i dd6 note 2 5.0 mhz crystal oscillation a/d operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 2.5 5.0 ma notes 1. the current flowing to av ref (a/d operation on (adcs0 = 1)), av dd current, and the port current (including the current flowing through the on-chip pull-up resistors) is not included. 2. the current flowing to av ref (a/d operation on (adcs0 = 1)) and the port current (including the current flowing through the on-chip pull-up resistors) is not included. for the current flowing to av ref , refer to the parameter of ?resistance between av ref and av ss ? in the 8-bit a/d converter characteristics and 10-bit a/d converter characteristics . 3. when the main system clock is stopped 4. high-speed mode operation (when processor clock control register (pcc) is set to 00h) 5. low-speed mode operation (when pcc is set to 02h) remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. chapter 21 electrical specifications 284 user?s manual u13952ej3v0ud lcd characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit vaon0 = 1 2.2 v dd v at 1/3 bias 2.7 v dd v lcd drive voltage v lcd vaon0 = 0 note 1 at 1/2 bias 3.0 v dd v when selecting 100 k ? by mask option 100 200 400 k ? lcd divider resistor note 2 r lcd when selecting 10 k ? by mask option 10 20 40 k ? lcd output voltage deviation note 3 (common) v odc i o = 5 av lcd0 = v lcd v lcd1 = v lcd 2/3 0 0.2 v lcd output voltage deviation note 3 (segment) v ods i o = 1 a 2.2 v v lcd v dd v lcd2 = v lcd 1/3 note 1 0 0.2 v notes 1. t a = ? 10 to +85 c in the normal mode (vaon0 = 0) 2. for mask rom version, 10 k ? , 100 k ? , or no divider resistor can be selected by mask option. the pd78f9418a has no divider resistor. 3. voltage deviation is the voltage difference between the ideal value of the segment or common output (v lcdn : n = 0 to 2) and the output voltage. flash memory write/erase characteristics ( pd78f9418a only) (t a = 10 to 40 c, v dd = 1.8 to 5.5 v, in 5.0 mhz crystal oscillation operating mode) parameter symbol conditions min. typ. max. unit write current note (v dd pin) i ddw when v pp supply voltage = v pp1 18 ma write current note (v pp pin) i ppw when v pp supply voltage = v pp1 22.5 ma erase current note (v dd pin) i dde when v pp supply voltage = v pp1 18 ma erase current note (v pp pin) i ppe when v pp supply voltage = v pp1 115 ma unit erase time t er 0.511s total erase time t era 20 s write count erase/write are regarded as 1 cycle 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v note the current flowing to the ports (including the current flowing through the on-chip pull-up resistors) is not included. chapter 21 electrical specifications user ? s manual u13952ej3v0ud 285 ac characteristics (1) basic operation (t a = ? ? ? ? 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 0.4 8 s operating with main system clock v dd = 1.8 to 5.5 v 1.6 8 s cycle time (minimum instruction execution time) t cy operating with subsystem clock 114 122 125 s v dd = 2.7 to 5.5 v 0 4 mhz ti0, ti1 input frequency f ti v dd = 1.8 to 5.5 v 0 275 khz v dd = 2.7 to 5.5 v 0.1 s ti0, ti1 input high-/ low-level widths t tih , t til v dd = 1.8 to 5.5 v 1.8 s interrupt input high-/ low-level widths t inth , t intl intp0 to intp3 10 s reset input low-level width t rsl 10 s t cy vs v dd (main system clock) 123456 0.1 0.4 1.0 10 60 guaranteed operating range cycle time [ s] supply voltage v dd [v] chapter 21 electrical specifications 286 user ? s manual u13952ej3v0ud (2) serial interface (t a = ? ? ? ? 40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (sck ... internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck cycle time t kcy1 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2 ? 50 ns sck high-/low-level widths t kh1 , t kl1 v dd = 1.8 to 5.5 v t kcy1 /2 ? 150 ns v dd = 2.7 to 5.5 v 150 ns si setup time (to sck ) t sik1 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si hold time (from sck ) t ksi1 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns so output delay time from sck t kso1 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and load capacitance of the so output line. (b) 3-wire serial i/o mode (sck ... external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 900 ns sck cycle time t kcy2 v dd = 1.8 to 5.5 v 3500 ns v dd = 2.7 to 5.5 v 400 ns sck high-/low-level widths t kh2 , t kl2 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si setup time (to sck ) t sik2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si hold time (from sck ) t ksi2 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns so output delay time from sck t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and load capacitance of the so output line. (c) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate v dd = 1.8 to 5.5 v 19531 bps chapter 21 electrical specifications user ? s manual u13952ej3v0ud 287 (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 900 ns asck cycle time t kcy3 v dd = 1.8 to 5.5 v 3500 ns v dd = 2.7 to 5.5 v 400 ns asck high-/low-level widths t kh3 , t kl3 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate v dd = 1.8 to 5.5 v 9766 bps asck rise/fall times t r , t f 1 s chapter 21 electrical specifications 288 user?s manual u13952ej3v0ud ac timing test points (excluding x1 and xt1 inputs) clock timing ti timing interrupt input timing reset input timing 0.8v dd 0.2v dd 0.8v dd 0.2v dd test points 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) 1/f xt t xtl t xth xt1 input v ih4 (min.) v il4 (max.) intp0 to intp3 t intl t inth reset t rsl ti0, ti1 t til 1/f ti t tih chapter 21 electrical specifications user ? s manual u13952ej3v0ud 289 serial transfer timing 3-wire serial i/o mode: remark m = 1 or 2 uart mode (external clock input): t kcym t klm t khm sck t sikm t ksim t ksom si so input data output data t kcy3 t kl3 t kh3 asck t r t f chapter 21 electrical specifications 290 user ? s manual u13952ej3v0ud 8-bit a/d converter characteristics ( pd789405a, 789406a, 789407a) (t a = ? ? ? ? 40 to +85 c, 1.8 v av ref av dd = v dd 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 888bit 2.7 v av ref av dd 5.5 v 0.4 0.6 %fsr overall error note 0.8 1.2 %fsr 2.7 v av ref av dd 5.5 v 14 100 s conversion time t conv 28 100 s analog input voltage v ian 0av ref v reference voltage av ref 1.8 av dd v resistance between av ref and av ss r adref 20 40 k ? note excludes quantization error ( 0.2%fsr). remark fsr: full-scale range 10-bit a/d converter characteristics ( pd789415a, 789416a, 789417a, 78f9418a) (t a = ? ? ? ? 40 to +85 c, 1.8 v av ref av dd = v dd 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.5 v av ref av dd 5.5 v 0.2 0.4 %fsr 2.7 v av ref av dd 5.5 v 0.4 0.6 %fsr overall error note 1.8 v av ref av dd 5.5 v 0.8 1.2 %fsr 4.5 v av ref av dd 5.5 v 14 100 s 2.7 v av ref av dd 5.5 v 14 100 s conversion time t conv 1.8 v av ref av dd 5.5 v 28 100 s 4.5 v av ref av dd 5.5 v 0.4 %fsr 2.7 v av ref av dd 5.5 v 0.6 %fsr zero-scale error note ainl 1.8 v av ref av dd 5.5 v 1.2 %fsr 4.5 v av ref av dd 5.5 v 0.4 %fsr 2.7 v av ref av dd 5.5 v 0.6 %fsr full-scale error note ainl 1.8 v av ref av dd 5.5 v 1.2 %fsr 4.5 v av ref av dd 5.5 v 2.5 lsb 2.7 v av ref av dd 5.5 v 4.5 lsb non-integral linearity note inl 1.8 v av ref av dd 5.5 v 8.5 lsb 4.5 v av ref av dd 5.5 v 1.5 lsb 2.7 v av ref av dd 5.5 v 2.0 lsb non-differential linearity note dnl 1.8 v av ref av dd 5.5 v 3.5 lsb analog input voltage v ian 0av ref v reference voltage av ref 1.8 av dd v resistance between av ref and av ss r adref 20 40 k ? note excludes quantization error ( 0.05%fsr). remark fsr: full-scale range chapter 21 electrical specifications user ? s manual u13952ej3v0ud 291 comparator characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit analog input range v cin 0v dd v v dd = 2.7 to 5.5 v 1.35 1.6 1.85 v reference voltage input range v cref v dd = 1.8 to 5.5 v 1.35 1.4 1.45 v accuracy 100 mv data memory stop mode low supply voltage data retention characteristics (t a = ? ? ? ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 15 /f x ms oscillation stabilization wait time note 1 t wait release by interrupt request note 2 ms notes 1. the oscillation stabilization wait time is the time after oscillation has started during which the cpu is stopped to prevent unstable operation. 2. selection of 2 12 /f x , 2 15 /f x , or 2 17 /f x is possible with bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time selection register (osts). remark fx: main system clock oscillation frequency chapter 21 electrical specifications 292 user ? s manual u13952ej3v0ud data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal) v dd stop mode t srel t wait stop instruction execution v dddr reset operation mode halt mode internal reset operation data retention mode v dd stop mode operation mode data retention mode halt mode t srel t wait v dddr stop instruction execution standby release signal (interrupt request) user?s manual u13952ej3v0ud 293 chapter 22 characteristics curves (reference values) 22.1 characteristics curves for mask rom versions 22 pf 33 pf v ss v ss crystal resonator 5.0 mhz crystal resonator 32.768 khz x1 xt1 xt2 x2 subsystem clock operation mode (css0 = 1) pcc = 00h subsystem clock operation halt mode (css0 = 1) supply voltage v dd (v) supply current i dd (ma) 10.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 (t a = 25 c) pcc = 02h pcc = 00h (halt mode) pcc = 02h (halt mode) 220 k ? 22 pf 33 pf chapter 22 characteristics cur ves (reference values) 294 user ? s manual u13952ej3v0ud v dd = 5.5 v 20 (t a = 25 c) 10 0 0 0.5 1.0 1.5 v dd - v oh ( v) 2.0 2.5 3.0 i oh vs v dd - v oh v dd = 4.0 v v dd = 4.5 v v dd = 5.0 v v dd = 3.5 v v dd = 3.0 v v dd = 2.5 v v dd = 2.0 v v dd = 1.8 v (t a = 25 c) 0 10 20 30 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 low-level output voltage v ol (v) low-level output current i ol (ma) high-level output current i oh (ma) i ol vs v ol v dd = 4.0 v v dd = 3.0 v v dd = 2.0 v v dd = 1.8 v v dd = 3.5 v v dd = 2.5 v v dd = 4.5 v v dd = 5.0 v v dd = 5.5 v chapter 22 characteristics cur ves (reference values) user ? s manual u13952ej3v0ud 295 22.2 characteristics curves for pd78f9418a 10.0 1.0 0.5 0.1 0.05 supply current i dd (ma) 0.01 0.005 0.001 012345678 x1 x2 crystal resonator 5.0 mhz 22 pf xt1 xt2 crystal resonator 32.768 khz 33 pf 220 k ? v ss 22 pf 33 pf v ss subsystem clock operation halt mode (css0 = 1, mcc = 1) subsystem clock operation mode (css0 = 1, mcc = 1) main system clock operation mode (pcc1 = 0, css0 = 0) main system clock operation mode (pcc1 = 1, css0 = 0) main system clock operation halt mode (pcc1 = 1, css0 = 0) main system clock operation halt mode (pcc1 = 0, css0 = 0) (t a = 25?c) supply voltage v dd (v) user?s manual u13952ej3v0ud 296 chapter 23 package drawings 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 ? 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 ? 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h chapter 23 package drawings user ? s manual u13952ej3v0ud 297 80-pin plastic tqfp (fine pitch) (12x12) item millimeters g h 0.22 0.05 1.25 a 14.0 0.2 c 12.0 0.2 d f 1.25 14.0 0.2 b 12.0 0.2 m n 0.08 0.145 0.05 p q 0.1 0.05 1.0 j 0.5 (t.p.) k l 0.5 1.0 0.2 i 0.08 s 1.1 0.1 r 3 + 4 ? 3 r h k l j f q g i t u s p detail of lead end note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. 60 41 40 21 61 80 120 m s s cd a b n m p80gk-50-9eu-1 t 0.25 u 0.6 0.15 user?s manual u13952ej3v0ud 298 chapter 24 recommended soldering conditions the pd789407a and pd789417a subseries should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) table 24-1. surface mounting type soldering conditions (1/2) pd789405agc- -8bt: 80-pin plastic qfp (14 14) pd789406agc- -8bt: 80-pin plastic qfp (14 14) pd789407agc- -8bt: 80-pin plastic qfp (14 14) pd789415agc- -8bt: 80-pin plastic qfp (14 14) pd789416agc- -8bt: 80-pin plastic qfp (14 14) pd789417agc- -8bt: 80-pin plastic qfp (14 14) pd78f9418agc-8bt: 80-pin plastic qfp (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: twice or less ir35-00-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: twice or less vp15-00-2 wave soldering soldering bath temperature: 260 c max., time: 10 seconds max., count: 1, preheating temperature: 120 c max. (package surface temperature) ws60-00-1 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? caution do not use different soldering methods together (except for partial heating). chapter 24 recommended soldering conditions user?s manual u13952ej3v0ud 299 table 24-1. surface mounting type soldering conditions (2/2) pd789405agk- -9eu: 80-pin plastic tqfp (fine pitch) (12 12) pd789406agk- -9eu: 80-pin plastic tqfp (fine pitch) (12 12) pd789407agk- -9eu: 80-pin plastic tqfp (fine pitch) (12 12) pd789415agk- -9eu: 80-pin plastic tqfp (fine pitch) (12 12) pd789416agk- -9eu: 80-pin plastic tqfp (fine pitch) (12 12) pd789417agk- -9eu: 80-pin plastic tqfp (fine pitch) (12 12) pd78f9418gk-9eu: 80-pin plastic tqfp (fine pitch) (12 12) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: twice or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) ir35-107-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: twice or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vp15-107-2 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). user?s manual u13952ej3v0ud 300 appendix a development tools the following development tools are available for development of systems using the pd789407a and pd789417a subseries. figure a-1 shows development tools. ? support of pc98-nx series unless specified otherwise, the products supported by ibm pc/at? compatibles can be used in the pc98-nx series. when using the pc98-nx series, refer to the explanation of ibm pc/at compatibles. ? windows unless specified otherwise, ?windows? indicates the following operating systems. ? windows 3.1 ? windows 95, 98, 2000 ? windows nt? ver.4.0 appendix a development tools user?s manual u13952ej3v0ud 301 figure a-1. development tools language processing software assembler package c compiler package device file c library source file note 1 debugging software integrated debugger system simulator host machine (pc or ews) interface adapter in-circuit emulator emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory writing adapter flash memory power supply unit software package control software project manager (windows version only) note 2 software package flash memory writing environment notes 1. c library source file is not included in the software package. 2. project manager is included in the assembler package. project manager is used only in the windows environment. appendix a development tools 302 user ? s manual u13952ej3v0ud a.1 software package software tools for development of the 78k/0s series are combined in this package. the following tools are included. ra78k0s, cc78k0s, id78k0s-ns, sm78k0s, and device files sp78k0s software package part number: s sp78k0s remark in the part number differs depending on the operating system to be used. s sp78k0s host machine os supply medium ab17 japanese windows cd-rom bb17 pc-9800 series, ibm pc/at compatibles english windows a.2 language processing software program that converts program written in mnemonic into object codes that can be executed by microcontroller. in addition, automatic functions to generate a symbol table and optimize branch instructions are also provided. used in combination with a device file (df789418) (sold separately). appendix a development tools user ? s manual u13952ej3v0ud 303 remark in the part number differs depending on the host machine and operating system to be used. s ra78k0s s cc78k0s host machine os supply medium ab13 japanese windows bb13 english windows 3.5-inch 2hd fd ab17 japanese windows bb17 pc-9800 series, ibm pc/at compatibles english windows 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) cd-rom s df789418 s cc78k0s-l host machine os supply medium ab13 japanese windows 3.5-inch 2hd fd bb13 pc-9800 series, ibm pc/at compatibles english windows 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 3.5-inch 2hd fd 3k15 sparcstation sunos (rel. 4.1.4), solaris (rel. 2.5.1) 1/4-inch cgmt a.3 control software project manager control software created for efficient development of the user program in the windows environment. user program development operations such as editor startup, build, and debugger startup can be performed from the project manager. appendix a development tools 304 user ? s manual u13952ej3v0ud a.5 debugging tools (hardware) ie-78k0s-ns in-circuit emulator in-circuit emulator for debugging a hardware and software of application system using the 78k/0s series. supports an integrated debugger (id78k0s-ns). used in combination with an ac adapter, emulation probe, and interface adapter for connecting the host machine. ie-78k0s-ns-a in-circuit emulator in-circuit emulator with functions expanded from the ie-78k0s-ns. the debug function has been further enhanced with the addition of a coverage function, and enhancement of the tracer function and timer function. ie-70000-mc-ps-b ac adapter adapter for supplying power from ac 100 to 240 v outlet. ie-70000-98-if-c interface adapter adapter necessary when using a pc-9800 series pc (except notebook type) as the host machine of the ie-78k0s-ns (c bus supported) ie-70000-cd-if-a pc card interface pc card and interface cable necessary when using a notebook pc as the host machine of the ie-78k0s-ns (pcmcia socket supported) ie-70000-pc-if-c interface adapter adapter necessary when using an ibm pc/at compatible as the host machine of the ie-78k0s-ns (isa bus supported) ie-70000-pci-if-a interface adapter adapter necessary when using a personal computer incorporating the pci bus as the host machine of the ie-78k0s-ns ie-789418-ns-em1 emulation board board for emulating the peripheral hardware specific to the device. used in combination with an in-circuit emulator. np-80gc emulation probe cable to connect an in-circuit emulator to the target system. used in combination with the ev-9200gc-80. ev-9200gc-80 conversion socket conversion socket to connect the np-80gc to a target system board on which an 80-pin plastic qfp (gc-8bt type) can be mounted. np-80gc-tq np-h80gc-tq emulation probe cable to connect an in-circuit emulator to the target system. used in combination with the tgc-080sbp. tgc-080sbp conversion adapter conversion adapter to connect the np-80gc-tq or np-h80gc-tq to a target system board on which an 80-pin plastic qfp (gc-8bt type) can be mounted. np-80gk np-h80gk-tq emulation probe cable to connect an in-circuit emulator to the target system. used in combination with the tgk-080sdw. tgk-080sdw conversion adapter conversion adapter to connect the np-80gk or np-h80gk-tq to a target system board on which an 80-pin plastic tqfp (fine pitch) (gk-9eu type) can be mounted. remarks 1. the np-80gc, np-80gc-tq, np-h80gc-tq, np-80gk, and np-h80gk-tq are products made by naito densei machida mfg. co., ltd. (tel +81-45-475-4191). 2. the tgc-080sbp and tgk-080sdw are products made by tokyo eletech corporation. for further information, contact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672) 3. the ev-9200gc-80 is sold in five units as a set. 4. the tgc-080sbp and tgk-080sdw are sold in one set units. appendix a development tools user ? s manual u13952ej3v0ud 305 a.6 debugging tools (software) this debugger supports the in-circuit emulators ie-78k0s-ns and ie-78k0s-ns-a for the 78k/0s series. the id78k0s-ns is windows-based software. it has improved c-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result. used in combination with a device file (df789418) (sold separately). id78k0s-ns integrated debugger part number: s id78k0s-ns this is a system simulator for the 78k/0s series. the sm78k0s is wi ndows-based software. it can be used to debug the target system at c source level or assembler level while simulating the operation of the target system on the host machine. using sm78k0s, the logic and performance of the application can be verified independently of hardware development. therefore, the development efficiency can be enhanced and the software quality can be improved. used in combination with a device file (df789418) (sold separately). sm78k0s system simulator part number: s sm78k0s file containing the information inherent to the device. used in combination with the ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s (all sold separately). df789418 note device file part number: s df789418 note df789418 is a common file that can be used with ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s. remark in the part number differs depending on the operating system and supply medium to be used. s id78k0s-ns s sm78k0s host machine os supply medium ab13 japanese windows bb13 english windows 3.5-inch 2hd fd ab17 japanese windows bb17 pc-9800 series, ibm pc/at compatibles english windows cd-rom appendix a development tools 306 user?s manual u13952ej3v0ud a.7 package drawings of conversion socket and conversion adapter a.7.1 package drawing and recommended footprint of conversion socket (ev-9200gc-80) figure a-2. package drawing of ev-9200gc-80 (for reference) a f d 1 no.1 pin index e ev-9200gc-80 b c m n o l k s r q p i h j g ev-9200gc-80-g1e item millimeters inches a b c d e f g h i j k l m n o p q r s 18.0 14.4 14.4 18.0 4-c 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.709 0.567 0.567 0.709 4-c 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014 0.091 0.059 based on ev-9200gc-80 (1) package drawing (in mm) appendix a development tools user ? s manual u13952ej3v0ud 307 figure a-3. recommended footprint of ev-9200gc-80 (for reference) a f d e c b g j k l h i 0.026 0.748=0.486 0.026 0.748=0.486 ev-9200gc-80-p1e item millimeters inches a b c d e f g h i j k l 19.7 15.0 15.0 19.7 6.0 0.05 6.0 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 0.776 0.591 0.591 0.776 0.236 0.236 0.014 0.093 0.091 0.062 0.65 0.02 19=12.35 0.05 0.65 0.02 19=12.35 0.05 +0.001 ? 0.002 +0.003 ? 0.002 +0.001 ? 0.002 +0.003 ? 0.002 +0.003 ? 0.002 +0.003 ? 0.002 +0.001 ? 0.001 +0.001 ? 0.002 +0.001 ? 0.002 based on ev-9200gc-80 (2) pad drawing (in mm) dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mount manual" (http://www.necel.com/pkg/en/mount/index.html). caution appendix a development tools 308 user ? s manual u13952ej3v0ud a.7.2 package drawing of conversion adapter (tgk-080sdw) figure a-4. package drawing of tgk-080sdw (for reference) item millimeters inches b 0.25 0.010 c 5.3 0.209 a 0.5x19=9.50.10 0.020x0.748=0.3740.004 d 5.3 0.209 h 1.850.2 0.0730.008 i 3.5 0.138 j 2.0 0.079 e 1.3 0.051 f 3.55 g 0.3 0.012 0.140 item millimeters inches b c 0.5x19=9.5 0.020x0.748=0.374 a 18.0 0.709 d h i 1.58 0.062 j 1.2 0.047 e 0.5x19=9.5 0.020x0.748=0.374 f 11.77 0.463 k 7.64 0.301 l 1.2 0.047 m q 1.2 0.047 r 1.58 0.062 s 3.55 0.140 n 1.58 0.062 o1.2 p 7.64 0.301 0.047 w 6.8 0.268 x 8.24 0.324 y 14.8 0.583 t c 2.0 c 0.079 u 12.31 v 10.17 0.400 0.485 z 1.40.2 0.0550.008 0.5 1.58 0.020 0.062 g 18.0 0.709 k 3.0 0.118 n 1.40.2 0.0550.008 o 1.40.2 0.0550.008 p h=1.8 1.3 h=0.071 0.051 l 0.25 m 14.0 0.551 0.010 q0~5 0.000~0.197 11.77 0.5 0.463 0.020 tgk-080sdw-g1e t 2.4 0.094 u 2.7 0.106 v 3.9 0.154 r 5.9 s 0.8 0.031 0.232 tgk-080sdw (tqpack080sd + tqsocket080sdw) package dimension (unit: mm) e f g p r q q q o o o n ijjj lllm b c a t h d k s m2 screw u a v e c d b w x y z m f r u t v g s k j i h l n o p protrusion : 4 places q note : product by tokyo eletech corporation. appendix a development tools user ? s manual u13952ej3v0ud 309 a.7.3 package drawing of conversion adapter (tgc-080sbp) figure a-5. package drawing of tgc-080sbp (for reference) item millimeters inches b 7.35 0.289 c 1.2 0.047 a (16.95) (0.667) d 1.85 0.073 e 3.5 0.138 f 2.0 g 6.0 0.236 0.079 item millimeters inches b 0.65x19=12.35 0.026x0.748=0.486 c 0.65 0.026 a 21.0 0.827 d h i c 2.0 c 0.079 14.47 0.570 j 14.95 0.589 e 12.75 0.502 f 15.15 0.596 k 13.95 0.549 l 13.7 0.539 m q 21.0 0.827 r 5.0 0.197 s n 1.15 0.045 o 12.62 p 17.52 0.690 0.497 w x y t u v z 10.35 1.15 0.407 0.045 g 17.55 0.691 reference diagram: tgc-080sbp (tqpack080sb+tqsocket080sbp) package dimension (unit: mm) note : product by tokyo eletech corporation. 1.8 0.071 4-c 1.0 4-c 0.039 7.7 0.303 4- 0.051 4- 1.3 ? 3.55 0.140 ? 5.3 0.209 ? 0.3 0.012 ? 0.9 0.035 ? h 0.25 0.010 i 13.95 j 1.025 0.040 0.549 k 1.025 0.040 l 2.4 0.094 m 2.7 0.106 tgc-080sbp-g0e cw i a b j k r u o p q h i x y z m l k j h d e g b a f g f l v m n e d protrusion height s t c 310 user?s manual u13952ej3v0ud appendix b notes on target system design figures b-1 to b-4 show the conditions when connecting the emulation probe to the conversion adapter or conversion socket. follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. (1) np-80gc, np-80gc-tq, np-h80gc-tq figure b-1. distance between in-circuit emulator and conversion socket (80gc) 170 mm note in-circuit emulator ie-78k0s-ns or ie-78k0s-ns-a emulation board ie-789418-ns-em1 conversion socket: ev-9200gc-80 or conversion adapter: tgc-080sbp target system cn1 emulation probe np-80gc, np-80gc-tq np-h80gc-tq note when np-h80gc-tq is used, the distance is 370 mm. remark np-80gc, np-80gc-tq, and np-h80gc-tq are products of naito densei machida mfg. co., ltd. appendix b notes on target system design user ? s manual u13952ej3v0ud 311 figure b-2. connection condition of target system (np-80gc-tq) target system 40 mm 23 mm 11 mm 34 mm extension probe np-80gc-tq emulation board ie-789418-ns-em1 conversion adapter tgc-080sbp remark np-80gc-tq is a product of naito densei machida mfg. co., ltd. tgc-080sbp is a product of tokyo eletech corporation. appendix b notes on target system design 312 user ? s manual u13952ej3v0ud (2) np-80gk, np-h80gk-tq figure b-3. distance between in-circuit emulator and conversion adapter (80gk) 170 mm note in-circuit emulator ie-78k0s-ns or ie-78k0s-ns-a emulation board ie-789418-ns-em1 conversion adapter tgk-080sdw target system cn1 emulation probe np-80gk, np-h80gk-tq note when np-h80gk-tq is used, the distance is 370 mm. remark np-80gk and np-h80gk-tq are products of naito densei machida mfg. co., ltd. tgk-080sdw is a product of tokyo eletech corporation. appendix b notes on target system design user ? s manual u13952ej3v0ud 313 figure b-4. connection condition of target system (np-80gk) target system 40 mm 23 mm 11 mm 34 mm extension probe np-80gk emulation board ie-789418-ns-em1 conversion adapter tgk-080sdw remark np-80gk is a product of naito densei machida mfg. co., ltd. tgk-080sdw is a product of tokyo eletech corporation. 314 user?s manual u13952ej3v0ud appendix c register index c.1 register index (alphabetic order of register name) [a] a/d conversion result register 0 (adcr0)....................................................................................... .............141, 154 a/d converter mode register 0 (adm0) ........................................................................................... .............143, 156 a/d input selection register 0 (ads0).......................................................................................... .................144, 157 asynchronous serial interface mode register 00 (asim00) ..........................................................177, 184, 186, 199 asynchronous serial interface status register 00 (asis00) ...................................................................... ....179, 187 [b] baud rate generator control register 00 (brgc00) ..............................................................................1 80, 188, 200 [c] comparator mode register 0 (cmprm0)............................................................................................ ..................168 [e] 8-bit compare register 00 (cr00) ............................................................................................... ..........................117 8-bit compare register 01 (cr01) ............................................................................................... ..........................117 8-bit compare register 02 (cr02) ............................................................................................... ..........................117 8-bit timer counter 00 (tm00) .................................................................................................. .............................117 8-bit timer counter 01 (tm01) .................................................................................................. .............................117 8-bit timer counter 02 (tm02) .................................................................................................. .............................117 8-bit timer mode control register 00 (tmc00)................................................................................... ....................118 8-bit timer mode control register 01 (tmc01)................................................................................... ....................119 8-bit timer mode control register 02 (tmc02)................................................................................... ....................120 external interrupt mode register 0 (intm0) ..................................................................................... .....................234 external interrupt mode register 1 (intm1) ..................................................................................... .....................235 [ i ] interrupt mask flag register 0 (mk0) ........................................................................................... ..........................233 interrupt mask flag register 1 (mk1) ........................................................................................... ..........................233 interrupt request flag register 0 (if0)........................................................................................ ............................232 interrupt request flag register 1 (if1)........................................................................................ ............................232 [k] key return mode register 00 (krm00)............................................................................................ ......................237 [l] lcd clock control register 0 (lcdc0) ........................................................................................... .......................207 lcd display mode register 0 (lcdm0)............................................................................................ .....................205 lcd port selector 0 (lps0) ..................................................................................................... .............................206 appendix c register index user?s manual u13952ej3v0ud 315 [o] oscillation stabilization time selection register (osts)....................................................................... ................. 245 [p] port 0 (p0).................................................................................................................... .......................................... 72 port 2 (p2).................................................................................................................... .......................................... 73 port 4 (p4).................................................................................................................... .......................................... 78 port 5 (p5).................................................................................................................... .......................................... 80 port 6 (p6).................................................................................................................... .......................................... 81 port 8 (p8).................................................................................................................... .......................................... 83 port 9 (p9).................................................................................................................... .......................................... 84 port mode register 0 (pm0) ..................................................................................................... ............................... 85 port mode register 2 (pm2) ..................................................................................................... ............... 85, 106, 121 port mode register 4 (pm4) ..................................................................................................... ............................... 85 port mode register 5 (pm5) ..................................................................................................... ............................... 85 port mode register 8 (pm8) ..................................................................................................... ............................... 85 port mode register 9 (pm9) ..................................................................................................... ............................... 85 processor clock control register (pcc) ......................................................................................... ......................... 91 pull-up resistor option register 0 (pu0) ....................................................................................... ........................... 86 pull-up resistor option register 1 (pu1) ....................................................................................... ........................... 86 pull-up resistor option register 2 (pu2) ....................................................................................... ........................... 86 [r] receive buffer register 00 (rxb00) ............................................................................................. ........................ 175 [s] serial operation mode register 00 (csim00)................................................................................ 176, 183, 185, 198 16-bit capture register 50 (tcp50)............................................................................................. .......................... 103 16-bit compare register 50 (cr50).............................................................................................. ......................... 103 16-bit timer counter 50 (tm50)................................................................................................. ............................ 103 16-bit timer mode control register 50 (tmc50) .................................................................................. .................. 104 subclock control register (css) ................................................................................................ ............................. 93 suboscillation mode register (sckm) ............................................................................................ ........................ 92 [t] timer clock selection register 2 (tcl2) ........................................................................................ ....................... 136 transmit shift register 00 (txs00) ............................................................................................. .......................... 175 [w] watch timer mode control register (wtm) ........................................................................................ ................... 131 watchdog timer mode register (wdtm)............................................................................................ ................... 137 appendix c register index 316 user?s manual u13952ej3v0ud c.2 register index (alphabetic order of register symbol) [a] adcr0: a/d conversion result register 0 ......................................................................................... ......141, 154 adm0: a/d converter mode register 0 ............................................................................................. ....143, 156 ads0: a/d input selection register 0 ............................................................................................ .......144, 157 asim00: asynchronous serial interface mode register 00 ......................................................177, 184, 186, 199 asis00: asynchronous serial interface status register 00 .....................................................................179 , 187 [b] brgc00: baud rate generator control register 00 ...........................................................................180, 1 88, 200 [c] cmprm0: comparator mode register 0 .............................................................................................. ..............168 cr00: 8-bit compare register 00 ................................................................................................. ................117 cr01: 8-bit compare register 01 ................................................................................................. ................117 cr02: 8-bit compare register 02 ................................................................................................. ................117 cr50: 16-bit compare register 50 ................................................................................................ ...............103 csim00: serial operation mode register 00 ............................................................................176, 183, 1 85, 198 css: subclock control register.................................................................................................. ..................93 [ i ] if0: interrupt request flag register 0 .......................................................................................... ..............232 if1: interrupt request flag register 1 .......................................................................................... ..............232 intm0: external interrupt mode register 0....................................................................................... .............234 intm1: external interrupt mode register 1....................................................................................... .............235 [k] krm00: key return mode register 00.............................................................................................. ...............237 [l] lcdc0: lcd clock control register 0 ............................................................................................. ................207 lcdm0: lcd display mode register 0.............................................................................................. ..............205 lps0: lcd port selector 0 ....................................................................................................... ...................206 [m] mk0: interrupt mask flag register 0 ............................................................................................. ..............233 mk1: interrupt mask flag register 1 ............................................................................................. ..............233 [o] osts: oscillation stabilization time selection register......................................................................... ........245 [p] p0: port 0...................................................................................................................... ............................72 p2: port 2...................................................................................................................... ............................73 p4: port 4...................................................................................................................... ............................78 p5: port 5...................................................................................................................... ............................80 p6: port 6...................................................................................................................... ............................81 appendix c register index user?s manual u13952ej3v0ud 317 p8: port 8 ...................................................................................................................... ........................... 83 p9: port 9 ...................................................................................................................... ........................... 84 pcc: processor clock control register........................................................................................... .............. 91 pm0: port mode register 0 ....................................................................................................... ................... 85 pm2: port mode register 2 ....................................................................................................... ... 85, 106, 121 pm4: port mode register 4 ....................................................................................................... ................... 85 pm5: port mode register 5 ....................................................................................................... ................... 85 pm8: port mode register 8 ....................................................................................................... ................... 85 pm9: port mode register 9 ....................................................................................................... ................... 85 pu0: pull-up resistor option register 0 ......................................................................................... ............... 86 pu1: pull-up resistor option register 1 ......................................................................................... ............... 86 pu2: pull-up resistor option register 2 ......................................................................................... ............... 86 [r] rxb00: receive buffer register 00............................................................................................... ................. 175 [s] sckm: suboscillation mode register.............................................................................................. ................ 92 [t] tcl2: timer clock selection register 2 .......................................................................................... ............. 136 tcp50: 16-bit capture register 50 ............................................................................................... .................. 103 tm00: 8-bit timer counter 00 .................................................................................................... ................... 117 tm01: 8-bit timer counter 01 .................................................................................................... ................... 117 tm02: 8-bit timer counter 02 .................................................................................................... ................... 117 tm50: 16-bit timer counter 50 ................................................................................................... .................. 103 tmc00: 8-bit timer mode control register 00 ..................................................................................... ............ 118 tmc01: 8-bit timer mode control register 01 ..................................................................................... ............ 119 tmc02: 8-bit timer mode control register 02 ..................................................................................... ............ 120 tmc50: 16-bit timer mode control register 50 .................................................................................... ........... 104 txs00: transmit shift register 00 ............................................................................................... .................. 175 [w] wdtm: watchdog timer mode register.............................................................................................. ........... 137 wtm: watch timer mode control register .......................................................................................... ......... 131 318 user?s manual u13952ej3v0ud appendix d revision history here is the revision history of this manual. the ?applied to:? column indicates the chapters of each edition in which the revision was applied. (1/2) edition revision from previous edition applied to: modification of packages ? deletion of 80-pin plastic tqfp (fine pitch) (gk-be9 type) ? addition of 80-pin plastic tqfp (fine pitch) (gk-9eu type) throughout modification of table 2-1 types of pin i/o circuits chapter 2 pin functions modification of table 4-3 port mode register and output latch settings when using alternate functions chapter 4 port functions modification of caution 2 in 6.2 configuration of 16-bit timer (1) 16-bit compare register 50 (cr50) modification of figure 6-2 format of 16-bit timer mode control register 50 addition of caution in 6.4.1 operation as timer interrupt modification of figure 6-8 settings of 16-bit timer mode control register 50 for capture operation chapter 6 16-bit timer addition of caution in 7.4.3 operation as square-wave output chapter 7 8-bit timer/ event counter addition of caution in 10.4.1 basic operation of 8-bit a/d converter chapter 10 8-bit a/d converter ( pd789407a subseries) addition of caution in 11.4.1 basic operation of 10-bit a/d converter chapter 11 10-bit a/d converter ( pd789417a subseries) addition of caution in table 18-1 differences between pd78f9418a and mask rom versions modification of table 18-2 communication mode and addition of note in it modification of figure 18-4 flashpro iii connection example in pseudo 3-wire mode (when p0 is used) modification of table 18-4 example of settings for pg-fp3 chapter 18 pd78f9418a modification of product name of flash memory programming adapter in a.2 flash memory programming tools 2nd addition of product name of conversion adapter corresponding to each emulation probe in a.3.1 hardware appendix a development tools modification of pin handling of av ref pin and v pp pin chapter 2 pin functions addition of note related to feedback resistor chapter 5 clock generator addition of 6.5 cautions on using 16-bit timer 50 chapter 6 16-bit timer 50 3rd addition of (8) input impedance of ani0 to ani6 pins in 10.5 cautions on using 8-bit a/d converter chapter 10 8-bit a/d converter ( pd789407a subseries) appendix d revision history user?s manual u13952ej3v0ud 319 (2/2) edition revision from previous edition applied to: modification of description of (2) a/d conversion result register 0 (adcr0) in 11.2 configuration of 10-bit a/d converter addition of (8) input impedance of ani0 to ani6 pins in 11.5 cautions on using 10-bit a/d converter chapter 11 10-bit a/d converter ( pd789417a subseries) addition of description on reading receive data of uart chapter 13 serial interface 00 addition of caution in figure 15-2 format of interrupt request flag register addition of caution in figure 15-7 format of key return mode register 00 chapter 15 interrupt functions addition of description on pull-up resistor and divider resistor for lcd driving in table 18-1 differences between pd78f9418a and mask rom versions overall revision of contents related to flash memory programming as 18.1 flash memory characteristics chapter 18 pd78f9418a addition of electrical specifications chapter 21 electrical specifications addition of characteristics curves (reference values) chapter 22 characteristics curves (reference values) addition of package drawings chapter 23 package drawings addition of recommended soldering conditions chapter 24 recommended soldering conditions overall revision of contents of development tools deletion of embedded software appendix a development tools 3rd addition of notes on target system design appendix b notes on target system design |
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